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Parameter Value
(37)
Default Description
FEEDBACK_TAP 6, 5, 14, 18,
28
6 Defines the feedback tap for the PRBS pattern generator and
checker. This is an intermediate stage that is XOR-ed with the
last stage to generate to next PRBS bit.
• If PRBS-7 is required, set this parameter to 6.
• If PRBS-9 is required, set this parameter to 5.
• If PRBS-15 is required, set this parameter to 14.
• If PRBS-23 is required, set this parameter to 18.
• If PRBS-31 is required, set this parameter to 28.
Table below lists the configuration that this design example supports. However, the design example
generated by the Qsys system is always fixed at a data rate of 6144 Mbps and a limited set of configuration
as shown in the table below. If your setting in the Qsys parameter editor does not match one of the LMF
and bonded mode parameter values in Table, the design example is generated with the default values of
LMF = 124.
Table 5-19: Static and Dynamic Reconfiguration Parameter Values Supported
Mode Link L M F Reference
Clock
Frame
Clock
Link
Clock
F1_
FRAMECLK_
DIV
F2_
FRAMECLK_
DIV
Static
Bonded/Non-bonded 2 1 1 2 153.6 153.6 153.6 2
Bonded/Non-bonded 1 1 1 4 153.6 153.6 153.6 1
Bonded/Non-bonded 1 1 2 4 153.6 153.6 153.6 1
Bonded/Non-bonded 1 1 4 8 153.6 76.8 153.6 1
Bonded/Non-bonded 1 2 1 1 153.6 153.6 153.6 4
Bonded/Non-bonded 1 2 1 2 153.6 153.6 153.6 2
Bonded/Non-bonded 1 2 1 4 153.6 153.6 153.6 1
Bonded/Non-bonded 2 2 2 2 153.6 153.6 153.6 2
Bonded/Non-bonded 1 2 2 4 153.6 153.6 153.6 1
Bonded/Non-bonded 1 2 4 4 153.6 153.6 153.6 1
Bonded/Non-bonded 1 4 2 1 153.6 153.6 153.6 4
Bonded/Non-bonded 1 4 2 2 153.6 153.6 153.6 2
Bonded/Non-bonded 1 4 4 2 153.6 153.6 153.6 2
Bonded/Non-bonded 1 4 4 4 153.6 153.6 153.6 1
Bonded/Non-bonded 1 4 8 4 153.6 153.6 153.6 1
(37)
Values supported or demonstrated by this design example.
UG-01142
2015.05.04
System Parameters
5-41
JESD204B IP Core Design Guidelines
Altera Corporation
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- JESD204B IP Core User Guide 1
- Contents 2
- Item Description 4
- Datapath Modes 8
- IP Core Variation 8
- Run-Time Configuration 9
- Channel Bonding 10
- About the JESD204B IP Core 13
- Getting Started 15
- Upgrading IP Cores 16
- IP Core Status Description 17
- Design Walkthrough 20
- Programming an FPGA Device 25
- Pin Assignments 26
- JESD204B IP Core Parameters 30
- Parameter Value Description 31
- JESD204B IP Core Testbench 35
- Configuration Preset Value 36
- Testbench Simulation Flow 37
- Subscribe 38
- Frame Clock 39
- Transmitter 41
- TX Data Link Layer 42
- Configura‐ 43
- Description 43
- MSB 6 5 4 3 2 1 LSB 43
- User Data Phase 44
- Receiver 45
- RX Data Link Layer 46
- Frame Alignment 47
- Lane Alignment 47
- ILAS Data 48
- Initial Lane Synchronization 48
- RX PHY Layer 49
- Operation 50
- Scrambler/Descrambler 51
- SYNC_N Signal 51
- Link Reinitialization 53
- Link Startup Sequence 54
- Device Clock 57
- Link Clock 58
- Local Multi-Frame Clock 59
- Clock Correlation 60
- Reset Scheme 61
- Reset Sequence 62
- Registers 80
- Access Type Definition 81
- Design Example Components 84
- PLL Reconfiguration 85
- Operation Avalon-MM 86
- Interface Signal 86
- Byte Address 86
- Offset (6bits) 86
- Bit Value 86
- Transceiver Reset Controller 87
- Pattern Generator 87
- Pattern Checker 88
- Transport Layer 89
- F Parameter f 90
- (txframe_clk frequency) f 90
- (rxframe_clk frequency) 90
- TX Path Data Remapping 100
- Altera Corporation 100
- Send Feedback 100
- UG-01142 104
- 2015.05.04 104
- F FRAMECLK_DIV TX Latency 105
- Parameter Description Value 106
- Related Information 113
- RX Path Data Remapping 114
- Serial Port Interface (SPI) 117
- Control Unit 118
- Memory Block (ROM) 119
- Finite State Machine (FSM) 120
- System Parameters 121
- Run-Time Reconfiguration 124
- System Interface Signals 125
- Signal Clock 128
- Direction Description 128
- PHY (Stratix V and Arria V) 133
- Implementation Guidelines 139
- Programmable RBD Offset 140
- Programmable LMFC Offset 143
- K K K K K RK K K K K 146
- D D D DK D D 146
- DK D DK K K 146
- Clocking Scheme 148
- JESD204B Parameters 148
- SPI Programming 149
- Additional Information 155
- Date Version Changes 156
- How to Contact Altera 157
- Contact Method Address 158
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