Altera JESD204B IP Manual de usuario Pagina 95
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Signal Clock Domain Direction Description
jesd204_tx_link_
datain[(L*32)-1:0]
txlink_clk Output Indicates transmitted data from the transport
layer to the DLL at txlink_clk clock rate, where
four octets are packed into a 32-bit data width per
lane. The data format is big endian. The table
below illustrates the data mapping for L = 4:
jesd204_tx_link_datain [x:y] Lane
[31:0] 0
[63:32] 1
[95:64] 2
[127:96] 3
Connect this signal to the TX DLL jesd204_tx_
link_data[] input pin.
jesd204_tx_link_
data_valid
txlink_clk Output
Indicates whether the jesd204_tx_link_
datain[] is valid or invalid.
• 0—jesd204_tx_link_datain[] is invalid
• 1—jesd204_tx_link_datain[] is valid
Connect this signal to the TX DLL jesd204_tx_
link_valid input pin.
jesd204_tx_link_
early_ready
(30)
txlink_clk
Input Indicates that the DLL requires valid data at the
subsequent implementation-specific duration.
Connect this signal to the TX DLL jesd204_tx_
frame_ready output pin.
jesd204_tx_link_
error
txlink_clk Output
Indicates an error at the Avalon-ST source
interface. Specifically, this signal is asserted when
jesd204_tx_data_valid = "0" while jesd204_
tx_data_ready = "1". The DLL subsequently
reports this error to the CSR block.
Connect this signal to the TX DLL jesd204_tx_
frame_error input pin.
Signal Clock Domain Direction Description
CSR in DLL
(30)
If a JESD device of No Multiple-Converter Device Alignment, Single-Lane (NMCDA-SL) class is deployed,
Altera recommends that you tie this input signal to "1".
5-14
TX Path
UG-01142
2015.05.04
Altera Corporation
JESD204B IP Core Design Guidelines
Send Feedback
- JESD204B IP Core User Guide 1
- Contents 2
- Item Description 4
- Datapath Modes 8
- IP Core Variation 8
- Run-Time Configuration 9
- Channel Bonding 10
- About the JESD204B IP Core 13
- Getting Started 15
- Upgrading IP Cores 16
- IP Core Status Description 17
- Design Walkthrough 20
- Programming an FPGA Device 25
- Pin Assignments 26
- JESD204B IP Core Parameters 30
- Parameter Value Description 31
- JESD204B IP Core Testbench 35
- Configuration Preset Value 36
- Testbench Simulation Flow 37
- Subscribe 38
- Frame Clock 39
- Transmitter 41
- TX Data Link Layer 42
- Configura‐ 43
- Description 43
- MSB 6 5 4 3 2 1 LSB 43
- User Data Phase 44
- Receiver 45
- RX Data Link Layer 46
- Frame Alignment 47
- Lane Alignment 47
- ILAS Data 48
- Initial Lane Synchronization 48
- RX PHY Layer 49
- Operation 50
- Scrambler/Descrambler 51
- SYNC_N Signal 51
- Link Reinitialization 53
- Link Startup Sequence 54
- Device Clock 57
- Link Clock 58
- Local Multi-Frame Clock 59
- Clock Correlation 60
- Reset Scheme 61
- Reset Sequence 62
- Registers 80
- Access Type Definition 81
- Design Example Components 84
- PLL Reconfiguration 85
- Operation Avalon-MM 86
- Interface Signal 86
- Byte Address 86
- Offset (6bits) 86
- Bit Value 86
- Transceiver Reset Controller 87
- Pattern Generator 87
- Pattern Checker 88
- Transport Layer 89
- F Parameter f 90
- (txframe_clk frequency) f 90
- (rxframe_clk frequency) 90
- TX Path Data Remapping 100
- Altera Corporation 100
- Send Feedback 100
- UG-01142 104
- 2015.05.04 104
- F FRAMECLK_DIV TX Latency 105
- Parameter Description Value 106
- Related Information 113
- RX Path Data Remapping 114
- Serial Port Interface (SPI) 117
- Control Unit 118
- Memory Block (ROM) 119
- Finite State Machine (FSM) 120
- System Parameters 121
- Run-Time Reconfiguration 124
- System Interface Signals 125
- Signal Clock 128
- Direction Description 128
- PHY (Stratix V and Arria V) 133
- Implementation Guidelines 139
- Programmable RBD Offset 140
- Programmable LMFC Offset 143
- K K K K K RK K K K K 146
- D D D DK D D 146
- DK D DK K K 146
- Clocking Scheme 148
- JESD204B Parameters 148
- SPI Programming 149
- Additional Information 155
- Date Version Changes 156
- How to Contact Altera 157
- Contact Method Address 158
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