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Table 2-5: JESD204B IP Core Resource Utilization
The numbers of ALMs and logic registers in this table are rounded up to the nearest 10.
Note: The resource utilization data are extracted from a full design which includes the Altera Transceiver PHY
Reset Controller IP Core. Thus, the actual resource utilization for the JESD204B IP core should be smaller
by about 15 ALMs and 20 registers.
Device Family Data Path Number of
Lanes
ALMs ALUTs Logic
Registers
Memory Block
(M10K/M20K)
(6)
(7)
Cyclone V
RX
1 1047 1543 1200 1
2 1594 2325 1825 2
4 2832 4043 3080 4
8 5354 7525 5585 8
TX
1 728 1148 948 0
2 889 1424 1066 0
4 1218 1941 1293 0
8 1715 2837 1757 0
Arria V
RX
1 1052 1543 1197 1
2 1586 2325 1823 2
4 2830 4043 3077 4
8 5330 7525 5584 8
TX
1 719 1148 947 0
2 887 1424 1062 0
4 1208 1941 1292 0
8 1724 2853 1754 0
Arria V GZ
RX
1 1062 1542 1215 0
2 1634 2363 1858 0
4 2934 4097 3141 0
8 5526 7697 5711 0
TX
1 728 1150 948 0
2 937 1488 1083 0
4 1365 2114 1354 0
8 2141 3417 1895 0
(6)
M10K for Arria V device, M20K for Arria V GZ, Stratix V and Arria 10 devices.
2-8
Performance and Resource Utilization
UG-01142
2015.05.04
Altera Corporation
About the JESD204B IP Core
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- JESD204B IP Core User Guide 1
- Contents 2
- Item Description 4
- Datapath Modes 8
- IP Core Variation 8
- Run-Time Configuration 9
- Channel Bonding 10
- About the JESD204B IP Core 13
- Getting Started 15
- Upgrading IP Cores 16
- IP Core Status Description 17
- Design Walkthrough 20
- Programming an FPGA Device 25
- Pin Assignments 26
- JESD204B IP Core Parameters 30
- Parameter Value Description 31
- JESD204B IP Core Testbench 35
- Configuration Preset Value 36
- Testbench Simulation Flow 37
- Subscribe 38
- Frame Clock 39
- Transmitter 41
- TX Data Link Layer 42
- Configura‐ 43
- Description 43
- MSB 6 5 4 3 2 1 LSB 43
- User Data Phase 44
- Receiver 45
- RX Data Link Layer 46
- Frame Alignment 47
- Lane Alignment 47
- ILAS Data 48
- Initial Lane Synchronization 48
- RX PHY Layer 49
- Operation 50
- Scrambler/Descrambler 51
- SYNC_N Signal 51
- Link Reinitialization 53
- Link Startup Sequence 54
- Device Clock 57
- Link Clock 58
- Local Multi-Frame Clock 59
- Clock Correlation 60
- Reset Scheme 61
- Reset Sequence 62
- Registers 80
- Access Type Definition 81
- Design Example Components 84
- PLL Reconfiguration 85
- Operation Avalon-MM 86
- Interface Signal 86
- Byte Address 86
- Offset (6bits) 86
- Bit Value 86
- Transceiver Reset Controller 87
- Pattern Generator 87
- Pattern Checker 88
- Transport Layer 89
- F Parameter f 90
- (txframe_clk frequency) f 90
- (rxframe_clk frequency) 90
- TX Path Data Remapping 100
- Altera Corporation 100
- Send Feedback 100
- UG-01142 104
- 2015.05.04 104
- F FRAMECLK_DIV TX Latency 105
- Parameter Description Value 106
- Related Information 113
- RX Path Data Remapping 114
- Serial Port Interface (SPI) 117
- Control Unit 118
- Memory Block (ROM) 119
- Finite State Machine (FSM) 120
- System Parameters 121
- Run-Time Reconfiguration 124
- System Interface Signals 125
- Signal Clock 128
- Direction Description 128
- PHY (Stratix V and Arria V) 133
- Implementation Guidelines 139
- Programmable RBD Offset 140
- Programmable LMFC Offset 143
- K K K K K RK K K K K 146
- D D D DK D D 146
- DK D DK K K 146
- Clocking Scheme 148
- JESD204B Parameters 148
- SPI Programming 149
- Additional Information 155
- Date Version Changes 156
- How to Contact Altera 157
- Contact Method Address 158
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