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Check these items:
• Review the schematic and board layout file to determine the polarity of the physical pin connection.
• Use assignment editor and pin planner to check the pin assignment and I/O standard for each pin.
• Use RTL viewer in the Quartus II software to verify that the top level port are connected to the lower
level module that you instantiate.
Debugging JESD204B Link Using SignalTap II and System Console
The SignalTap II provides dynamic view of signals while the system console provides access to the
JESD204B IP core register sets through the Avalon-MM interfaces.
The SignalTap II and system console are very useful tools in debugging the JESD204B link related issues.
To use the system console, your design must contain a Qsys subsystem with the JTAG-to-Avalon-MM
Master bridge component and the Merlin slave translator ports that connect to the JESD204B IP core
Avalon-MM interface.
PHY Layer
Verify the RX PHY status through these signals in the <ip_variant_name>.v:
• rx_is_lockedtodata
• rx_analogreset
• rx_digitalreset
• rx_cal_busy
Verify the TX PHY status through these signals in the <ip_variant_name>.v:
• pll_locked
• pll_powerdown
• tx_analogreset
• tx_digitalreset
• tx_cal_busy
Verify the RX_TX PHY status through these signals in the <ip_variant_name>.v:
• rx_is_lockedtodata
• rx_analogreset
• rx_digitalreset
• rx_cal_busy
• rx_seriallpbken
• pll_locked
• pll_powerdown
• tx_analogreset
• tx_digitalreset
• tx_cal_busy
Use the rxphy_clk[0] or txphy_clk[0] signal as sampling clock for the SignalTap II.
For a normal operation of the JESD204B RX path, the rx_is_lockedtodata bit for each lane should be
"1" while the rx_cal_busy, rx_analogreset, and rx_digitalreset bit for each lane should be "0".
For a normal operation of the JESD204B TX path, the pll_locked bit for each lane should be "1" while
the tx_cal_busy, pll_powerdown, tx_analogreset, and tx_digitalreset bit for each lane should be
"0".
UG-01142
2015.05.04
Debugging JESD204B Link Using SignalTap II and System Console
7-3
JESD204B IP Core Debug Guidelines
Altera Corporation
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- JESD204B IP Core User Guide 1
- Contents 2
- Item Description 4
- Datapath Modes 8
- IP Core Variation 8
- Run-Time Configuration 9
- Channel Bonding 10
- About the JESD204B IP Core 13
- Getting Started 15
- Upgrading IP Cores 16
- IP Core Status Description 17
- Design Walkthrough 20
- Programming an FPGA Device 25
- Pin Assignments 26
- JESD204B IP Core Parameters 30
- Parameter Value Description 31
- JESD204B IP Core Testbench 35
- Configuration Preset Value 36
- Testbench Simulation Flow 37
- Subscribe 38
- Frame Clock 39
- Transmitter 41
- TX Data Link Layer 42
- Configura‐ 43
- Description 43
- MSB 6 5 4 3 2 1 LSB 43
- User Data Phase 44
- Receiver 45
- RX Data Link Layer 46
- Frame Alignment 47
- Lane Alignment 47
- ILAS Data 48
- Initial Lane Synchronization 48
- RX PHY Layer 49
- Operation 50
- Scrambler/Descrambler 51
- SYNC_N Signal 51
- Link Reinitialization 53
- Link Startup Sequence 54
- Device Clock 57
- Link Clock 58
- Local Multi-Frame Clock 59
- Clock Correlation 60
- Reset Scheme 61
- Reset Sequence 62
- Registers 80
- Access Type Definition 81
- Design Example Components 84
- PLL Reconfiguration 85
- Operation Avalon-MM 86
- Interface Signal 86
- Byte Address 86
- Offset (6bits) 86
- Bit Value 86
- Transceiver Reset Controller 87
- Pattern Generator 87
- Pattern Checker 88
- Transport Layer 89
- F Parameter f 90
- (txframe_clk frequency) f 90
- (rxframe_clk frequency) 90
- TX Path Data Remapping 100
- Altera Corporation 100
- Send Feedback 100
- UG-01142 104
- 2015.05.04 104
- F FRAMECLK_DIV TX Latency 105
- Parameter Description Value 106
- Related Information 113
- RX Path Data Remapping 114
- Serial Port Interface (SPI) 117
- Control Unit 118
- Memory Block (ROM) 119
- Finite State Machine (FSM) 120
- System Parameters 121
- Run-Time Reconfiguration 124
- System Interface Signals 125
- Signal Clock 128
- Direction Description 128
- PHY (Stratix V and Arria V) 133
- Implementation Guidelines 139
- Programmable RBD Offset 140
- Programmable LMFC Offset 143
- K K K K K RK K K K K 146
- D D D DK D D 146
- DK D DK K K 146
- Clocking Scheme 148
- JESD204B Parameters 148
- SPI Programming 149
- Additional Information 155
- Date Version Changes 156
- How to Contact Altera 157
- Contact Method Address 158
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