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Parameter Description Value
F1_FRAMECLK_
DIV
Only applies to cases where F=1.
The divider ratio on the frame_clk. The assembler always use the
post-divided frame_clk (txframe_clk).
(29)
1, 4
F2_FRAMECLK_
DIV
Only applies to cases where F=2.
The divider ratio on the frame_clk. The assembler always use the
post-divided frame_clk (txframe_clk).
(29)
1, 2
RECONFIG_EN Enable reconfiguration support in the transport layer. Only
downscaling reconfiguration is supported. Disable the reconfiguration
to reduce the logic.
0, 1
DATA_BUS_
WIDTH
The data input bus width size that depends on the F and L.
bus_width = M*S*N
F = (M*S*N_PRIME)/(8*L)
M*S = (8*F*L)/N_PRIME
Therefore the data bus width = (8*F*L*N)/N_PRIME
(8*F*L*N)/
N_PRIME
CONTROL_BUS_
WIDTH
The control output bus width size. The width depends on the CS
parameter as well as the M and S parameters. When CS is 0, the
control data is one bit wide (tie the signal to 0).
If CS = 0, the bus width = 1. Otherwise, the bus width = (OUTPUT_
BUS_WIDTH/N*CS) while OUTPUT_BUS_WIDTH/N = M*S
OUTPUT_
BUS_
WIDTH/
N*CS
Table 5-5: Assembler Signals
Signal Clock Domain Direction Description
Control Unit
txlink_clk
— Input
TX link clock signal. This clock is equal to the TX
data rate divided by 40. This clock is synchronous
to the txframe_clk signal.
txframe_clk
— Input
TX frame clock used by the transport layer. The
frequency is a function of parameters F, F1_
FRAMECLK_DIV, F2_FRAMECLK_DIV and
txlink_clk.
This clock is synchronous to the txlink_clk
signal.
(29)
Refer to the Table 5-7 to set the desired frame clock frequency with different FRAMECLK_DIV and F
values.
5-12
TX Path
UG-01142
2015.05.04
Altera Corporation
JESD204B IP Core Design Guidelines
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- JESD204B IP Core User Guide 1
- Contents 2
- Item Description 4
- Datapath Modes 8
- IP Core Variation 8
- Run-Time Configuration 9
- Channel Bonding 10
- About the JESD204B IP Core 13
- Getting Started 15
- Upgrading IP Cores 16
- IP Core Status Description 17
- Design Walkthrough 20
- Programming an FPGA Device 25
- Pin Assignments 26
- JESD204B IP Core Parameters 30
- Parameter Value Description 31
- JESD204B IP Core Testbench 35
- Configuration Preset Value 36
- Testbench Simulation Flow 37
- Subscribe 38
- Frame Clock 39
- Transmitter 41
- TX Data Link Layer 42
- Configura‐ 43
- Description 43
- MSB 6 5 4 3 2 1 LSB 43
- User Data Phase 44
- Receiver 45
- RX Data Link Layer 46
- Frame Alignment 47
- Lane Alignment 47
- ILAS Data 48
- Initial Lane Synchronization 48
- RX PHY Layer 49
- Operation 50
- Scrambler/Descrambler 51
- SYNC_N Signal 51
- Link Reinitialization 53
- Link Startup Sequence 54
- Device Clock 57
- Link Clock 58
- Local Multi-Frame Clock 59
- Clock Correlation 60
- Reset Scheme 61
- Reset Sequence 62
- Registers 80
- Access Type Definition 81
- Design Example Components 84
- PLL Reconfiguration 85
- Operation Avalon-MM 86
- Interface Signal 86
- Byte Address 86
- Offset (6bits) 86
- Bit Value 86
- Transceiver Reset Controller 87
- Pattern Generator 87
- Pattern Checker 88
- Transport Layer 89
- F Parameter f 90
- (txframe_clk frequency) f 90
- (rxframe_clk frequency) 90
- TX Path Data Remapping 100
- Altera Corporation 100
- Send Feedback 100
- UG-01142 104
- 2015.05.04 104
- F FRAMECLK_DIV TX Latency 105
- Parameter Description Value 106
- Related Information 113
- RX Path Data Remapping 114
- Serial Port Interface (SPI) 117
- Control Unit 118
- Memory Block (ROM) 119
- Finite State Machine (FSM) 120
- System Parameters 121
- Run-Time Reconfiguration 124
- System Interface Signals 125
- Signal Clock 128
- Direction Description 128
- PHY (Stratix V and Arria V) 133
- Implementation Guidelines 139
- Programmable RBD Offset 140
- Programmable LMFC Offset 143
- K K K K K RK K K K K 146
- D D D DK D D 146
- DK D DK K K 146
- Clocking Scheme 148
- JESD204B Parameters 148
- SPI Programming 149
- Additional Information 155
- Date Version Changes 156
- How to Contact Altera 157
- Contact Method Address 158
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