Altera JESD204B IP Manual de usuario Pagina 85
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Related Information
• Clocking Scheme on page 4-18
More information about the JESD204B IP core clocks.
PLL Reconfiguration
The PLL reconfiguration utilizes the ALTERA_PLL_RECONFIG IP core to implement reconfiguration
logic to facilitate dynamic real-time reconfiguration of PLLs in Altera devices. You can use this megafunc‐
tion IP core to update the output clock frequency, PLL bandwidth, and phase shifts in real time, without
reconfiguring the entire FPGA.
The design example uses the MIF approach to reconfigure the core PLL. The ALTERA_PLL_RECONFIG
IP core has two parameter options—Enable MIF Streaming and Path to MIF file—for the MIF input.
Turn on Enable MIF Streaming option and set the core_pll.mif as the value to Path to MIF file
parameter.
The following PLL reconfiguration Avalon-MM operations occurs during data rate reconfiguration.
Table 5-1: PLL Reconfiguration Operation
Operation Avalon-MM
Interface
Signal
Byte
Address
Offset
(6bits)
Bit Value
Arria V and Stratix V Devices
Set MIF base address pll_mgmt_* 0x01F [8:0] 0x000 (maximum configuration)
or
0x02E (downscale configuration)
Write to the START register to
begin
pll_mgmt_* 0x02 [0:0] 0x01
Arria 10 Devices
Start MIF streaming with MIF
base address specified in data
value
pll_mgmt_* 0x010 [31:0] 0x000 (maximum configuration)
or
0x02E (downscale configuration)
(28)
Related Information
AN 661: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig
Megafunctions
More information about the MIF streaming option.
Transceiver Reconfiguration Controller
The transceiver reconfiguration controller allows you to change the device transceiver settings at any
time. Any portion of the transceiver can be selectively reconfigured. Each portion of the reconfiguration
(28)
The MIF base address is 9 bits (LSB). The remaining bits are reserved.
5-4
PLL Reconfiguration
UG-01142
2015.05.04
Altera Corporation
JESD204B IP Core Design Guidelines
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- JESD204B IP Core User Guide 1
- Contents 2
- Item Description 4
- Datapath Modes 8
- IP Core Variation 8
- Run-Time Configuration 9
- Channel Bonding 10
- About the JESD204B IP Core 13
- Getting Started 15
- Upgrading IP Cores 16
- IP Core Status Description 17
- Design Walkthrough 20
- Programming an FPGA Device 25
- Pin Assignments 26
- JESD204B IP Core Parameters 30
- Parameter Value Description 31
- JESD204B IP Core Testbench 35
- Configuration Preset Value 36
- Testbench Simulation Flow 37
- Subscribe 38
- Frame Clock 39
- Transmitter 41
- TX Data Link Layer 42
- Configura‐ 43
- Description 43
- MSB 6 5 4 3 2 1 LSB 43
- User Data Phase 44
- Receiver 45
- RX Data Link Layer 46
- Frame Alignment 47
- Lane Alignment 47
- ILAS Data 48
- Initial Lane Synchronization 48
- RX PHY Layer 49
- Operation 50
- Scrambler/Descrambler 51
- SYNC_N Signal 51
- Link Reinitialization 53
- Link Startup Sequence 54
- Device Clock 57
- Link Clock 58
- Local Multi-Frame Clock 59
- Clock Correlation 60
- Reset Scheme 61
- Reset Sequence 62
- Registers 80
- Access Type Definition 81
- Design Example Components 84
- PLL Reconfiguration 85
- Operation Avalon-MM 86
- Interface Signal 86
- Byte Address 86
- Offset (6bits) 86
- Bit Value 86
- Transceiver Reset Controller 87
- Pattern Generator 87
- Pattern Checker 88
- Transport Layer 89
- F Parameter f 90
- (txframe_clk frequency) f 90
- (rxframe_clk frequency) 90
- TX Path Data Remapping 100
- Altera Corporation 100
- Send Feedback 100
- UG-01142 104
- 2015.05.04 104
- F FRAMECLK_DIV TX Latency 105
- Parameter Description Value 106
- Related Information 113
- RX Path Data Remapping 114
- Serial Port Interface (SPI) 117
- Control Unit 118
- Memory Block (ROM) 119
- Finite State Machine (FSM) 120
- System Parameters 121
- Run-Time Reconfiguration 124
- System Interface Signals 125
- Signal Clock 128
- Direction Description 128
- PHY (Stratix V and Arria V) 133
- Implementation Guidelines 139
- Programmable RBD Offset 140
- Programmable LMFC Offset 143
- K K K K K RK K K K K 146
- D D D DK D D 146
- DK D DK K K 146
- Clocking Scheme 148
- JESD204B Parameters 148
- SPI Programming 149
- Additional Information 155
- Date Version Changes 156
- How to Contact Altera 157
- Contact Method Address 158
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