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You should set a safe LMFC offset value to ensure deterministic latency from one power cycle to another
power cycle. In Figure 6-6, the illegal csr_lmfc_offset values of 1, 2, and 3 will cause lane de-skew error
because the RBD buffer size has exceeded.
Figure 6-6: Selecting Illegal LMFC Offset Value for RX, Causing Lane Deskew Error
First LMFC
boundary
SYSREF pulse is
sampled by IP core ‘s
internal register
2 link clock cycle deterministic
delay from SYSREF sampled
high to the first LMFC boundary
Free running LMFC counter
Internal
LMFC Counter
0 1 2 0 1 4 0 1 2 3 4 5 6 7
K
SYNC_N deasserted at LMFC boundary
K K K K RK K K K K
Latest arrival
lane in multiple
power cycles
D D D D
0
Power cycle variation
Fourth LMFC
boundary
1 link clock period = LMFC count
Internal LMFC counter resets
csr_lmfc_offset=0
7
Third LMFC
boundary
D D
SYNC_N
transmitted by RX
R R
Free running LMFC counter
Internal
LMFC Counter
3 4 5 6 7 0 1 3 4 5 6 7 0 1 2
3
RBD elastic buffer
released
when csr _rbd_offset=0
2
K K K K KK K K K K
Internal LMFC counter resets
csr_lmfc_offset=3
LMFC boundary is
delayed by 5 link clock
First LMFC boundary
at new location
R D D D D D DR R
6
1
K
K
Latest arrival
lane in multiple
power cycles
K K K K K RK K K K K
Earliest arrival
lane
D D D
D
D D
K
5
RBD elastic buffer size = 8
D D D
RBD elastic buffer
size is exceeded
rx_sysref
Third LMFC boundary at new location
You can use the TX LMFC offset to align the LMFC counter in IP core to the LMFC counter in DAC.
UG-01142
2015.05.04
Programmable LMFC Offset
6-7
JESD204B IP Core Deterministic Latency Implementation Guidelines
Altera Corporation
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- JESD204B IP Core User Guide 1
- Contents 2
- Item Description 4
- Datapath Modes 8
- IP Core Variation 8
- Run-Time Configuration 9
- Channel Bonding 10
- About the JESD204B IP Core 13
- Getting Started 15
- Upgrading IP Cores 16
- IP Core Status Description 17
- Design Walkthrough 20
- Programming an FPGA Device 25
- Pin Assignments 26
- JESD204B IP Core Parameters 30
- Parameter Value Description 31
- JESD204B IP Core Testbench 35
- Configuration Preset Value 36
- Testbench Simulation Flow 37
- Subscribe 38
- Frame Clock 39
- Transmitter 41
- TX Data Link Layer 42
- Configura‐ 43
- Description 43
- MSB 6 5 4 3 2 1 LSB 43
- User Data Phase 44
- Receiver 45
- RX Data Link Layer 46
- Frame Alignment 47
- Lane Alignment 47
- ILAS Data 48
- Initial Lane Synchronization 48
- RX PHY Layer 49
- Operation 50
- Scrambler/Descrambler 51
- SYNC_N Signal 51
- Link Reinitialization 53
- Link Startup Sequence 54
- Device Clock 57
- Link Clock 58
- Local Multi-Frame Clock 59
- Clock Correlation 60
- Reset Scheme 61
- Reset Sequence 62
- Registers 80
- Access Type Definition 81
- Design Example Components 84
- PLL Reconfiguration 85
- Operation Avalon-MM 86
- Interface Signal 86
- Byte Address 86
- Offset (6bits) 86
- Bit Value 86
- Transceiver Reset Controller 87
- Pattern Generator 87
- Pattern Checker 88
- Transport Layer 89
- F Parameter f 90
- (txframe_clk frequency) f 90
- (rxframe_clk frequency) 90
- TX Path Data Remapping 100
- Altera Corporation 100
- Send Feedback 100
- UG-01142 104
- 2015.05.04 104
- F FRAMECLK_DIV TX Latency 105
- Parameter Description Value 106
- Related Information 113
- RX Path Data Remapping 114
- Serial Port Interface (SPI) 117
- Control Unit 118
- Memory Block (ROM) 119
- Finite State Machine (FSM) 120
- System Parameters 121
- Run-Time Reconfiguration 124
- System Interface Signals 125
- Signal Clock 128
- Direction Description 128
- PHY (Stratix V and Arria V) 133
- Implementation Guidelines 139
- Programmable RBD Offset 140
- Programmable LMFC Offset 143
- K K K K K RK K K K K 146
- D D D DK D D 146
- DK D DK K K 146
- Clocking Scheme 148
- JESD204B Parameters 148
- SPI Programming 149
- Additional Information 155
- Date Version Changes 156
- How to Contact Altera 157
- Contact Method Address 158
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