Altera 100G Interlaken MegaCore Function Manual de usuario Pagina 78
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Offset Name R/W Description
9'h10
PLL_LOCKED
RO In Arria 10 devices: [0] – Transmit PLL lock indication.
In other device families: [Number of transceiver blocks–1:0]
– Transceiver block transmit PLL n lock indication. One
lock indicator per transceiver block. Bits that correspond to
unused transceiver block PLLs are forced to 1.
9'h11
FREQ_LOCKED
RO [NUM_LANES–1:0] – Clock data recovery is frequency
locked on the inbound data stream
9'h12
LOOPBACK
RW [NUM_LANES–1:0] – For each lane, write a 1 to activate
internal TX to RX serial loopback mode, or write a 0 to
disable the loopback for normal operation.
9'h13
RESET
RW Bit 9 : 1 = Force lock to data mode
Bit 8 : 1 =Force lock to reference mode
Bit 7 : 1 = Synchronously clear the TX-side error counters
and sticky flags
Bit 6 : 1 = Synchronously clear the RX-side error counters
and sticky flags
Bit 5 : 1 =Program load mode: perform a sequence of DMA
reads. Currently the IP core supports only the value of 1'b0,
indicating a processor controls the read operations.
Bit 4 : 1 = Ignore the RX analog reset
Bit 3 : 1 = Reset the soft microcontroller
Bit 2 : 1 = Reset the transmitter and the receiver
Bit 1 : 1 = Reset the receiver
Bit 0 : 1 =Ignore RX digital resets
The normal operating state for this register is all zeroes, to
allow automatic reset control. These bits are intended
primarily for hardware debugging use. Bit 2 is a good
general purpose soft reset. Bits 6 and 7 are convenient for
monitoring long stretches of error-free operation.
9'h20
ALIGN
RO Bit 12 : TX lanes are aligned
Bit 0 : RX lanes are aligned.
9'h21
WORD_LOCK
RO [NUM_LANES–1:0] – Word (block) boundaries have been
identified in the RX stream.
9'h22
SYNC_LOCK
RO [NUM_LANES–1:0] – Metaframe synchronization has been
achieved.
UG-01128
2015.05.04
100G Interlaken IP Core Register Map
6-3
100G Interlaken IP Core Register Map
Altera Corporation
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- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About This MegaCore Function 3
- Device Family Support 6
- IP Core Verification 7
- Device Speed Grade Support 9
- Release Information 9
- Altera IP Core Release Notes 10
- OpenCore Plus IP Evaluation 11
- - HDL synthesis file 13
- 10 variation 14
- Pin Assignments 16
- Adding the External PLL 22
- 100G Interlaken IP Core 23
- Number of Lanes 25
- Meta Frame Length in Words 26
- Data Rate 26
- Enable M20K ECC Support 28
- Include Diagnostic Features 28
- Number of Calendar Pages 29
- TX Scrambler Seed 29
- Transfer Mode Selection 30
- Data Format 30
- Functional Description 31
- Management Interface 32
- High Level Block Diagram 34
- IP Core Reset 35
- Interleaved and Packet Modes 37
- Dual Segment Mode 38
- M20K ECC Support 40
- Device Dependent Signals 72
- Offset Name R/W Description 76
- Example Design 82
- Top Testbench 82
- Testbench Simulation Behavior 83
- Simulating the Example Design 84
- Internal Serial Loopback Mode 86
- External Loopback Mode 87
- CRC32 Error Injection 92
- CRC24 Error Injection 93
- Advanced Parameter Settings 94
- RXFIFO Address Width 95
- Subscribe 98
- UG-01128 100
- 2015.05.04 100
- Signal Name Direction Width 102
- Description 102
- Related Information 102
- Ethernet Traffic 103
- Altera Corporation 105
- Send Feedback 105
- Additional Information 106
- Date ACDS 107
- Changes Made 107
- How to Contact Altera 110
- Typographic Conventions 110
- Visual Cue Meaning 111
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