Altera 100G Interlaken MegaCore Function Manual de usuario Pagina 31
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Functional Description
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2015.05.04
UG-01128
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The 100G Interlaken MegaCore function provides the functionality described in the Interlaken Protocol
Specification, Revision 1.2.
Related Information
Interlaken Protocol Specification, Revision 1.2
Interfaces Overview
The Altera 100G Interlaken MegaCore function supports the following interfaces:
Application Interface on page 4-1
Interlaken Interface on page 4-1
Out-of-Band Flow Control Interface on page 4-2
Management Interface on page 4-2
Transceiver Control Interfaces on page 4-2
Application Interface
The application interface, also called the user data transfer interface, provides up to 256 channels of
communication to and from the Interlaken link.
Related Information
• High Level Block Diagram on page 4-4
The figure lists the major application interface signals.
• 100G Interlaken IP Core User Data Transfer Interface Signals on page 5-4
Comprehensive list of application interface signals and information about required signal behavior.
Interlaken Interface
The Interlaken interface complies with the Interlaken Protocol Specification, Revision 1.2. It provides a
high-speed transceiver interface to an Interlaken link.
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of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
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product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
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101 Innovation Drive, San Jose, CA 95134
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About This MegaCore Function 3
- Device Family Support 6
- IP Core Verification 7
- Device Speed Grade Support 9
- Release Information 9
- Altera IP Core Release Notes 10
- OpenCore Plus IP Evaluation 11
- - HDL synthesis file 13
- 10 variation 14
- Pin Assignments 16
- Adding the External PLL 22
- 100G Interlaken IP Core 23
- Number of Lanes 25
- Meta Frame Length in Words 26
- Data Rate 26
- Enable M20K ECC Support 28
- Include Diagnostic Features 28
- Number of Calendar Pages 29
- TX Scrambler Seed 29
- Transfer Mode Selection 30
- Data Format 30
- Functional Description 31
- Management Interface 32
- High Level Block Diagram 34
- IP Core Reset 35
- Interleaved and Packet Modes 37
- Dual Segment Mode 38
- M20K ECC Support 40
- Device Dependent Signals 72
- Offset Name R/W Description 76
- Example Design 82
- Top Testbench 82
- Testbench Simulation Behavior 83
- Simulating the Example Design 84
- Internal Serial Loopback Mode 86
- External Loopback Mode 87
- CRC32 Error Injection 92
- CRC24 Error Injection 93
- Advanced Parameter Settings 94
- RXFIFO Address Width 95
- Subscribe 98
- UG-01128 100
- 2015.05.04 100
- Signal Name Direction Width 102
- Description 102
- Related Information 102
- Ethernet Traffic 103
- Altera Corporation 105
- Send Feedback 105
- Additional Information 106
- Date ACDS 107
- Changes Made 107
- How to Contact Altera 110
- Typographic Conventions 110
- Visual Cue Meaning 111
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