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packet transfer, the packet is not interleaved with another packet. In this case, the IP core still asserts the
irx_sob and irx_eob signals correctly to maintain the proper burst boundaries.
Related Information
Dual Segment Mode on page 4-8
100G Interlaken IP Core RX Errored Packet Handling
The 100G Interlaken IP Core provides information about errored packets on the RX user data transfer
interface through the following output signals:
• irx_eopbits[3:0]—If this signal has the value of 4'b0001, an error indication arrived with the packet
on the incoming Interlaken link: the EOP_Format field of the control word following the final burst of
the packet on the Interlaken link has this value, which indicates an error and EOP.
• irx_err—If you turn on Include advanced error reporting and handling, the 100G Interlaken IP
Core checks the integrity of incoming packets on the Interlaken link, and reports the packet corruption
errors it detects on the RX user data transfer interface in the irx_err output signal.
In both cases, the application is responsible for discarding the relevant packet.
If you turn on Include advanced error reporting and handling, the irx_err signal reflects the following
errors:
• CRC24 errors
• Loss of lane alignment
• Illegal control word
• Illegal framing pattern
• Missing SOP or EOP indicator
If you turn on Include advanced error reporting and handling, the irx_err output signal is aligned with
irx_eopbits, and is always asserted when irx_eopbits has the value of 4'b0001. However, irx_eopbits
can have the value of 4'b0001 when irx_err is not asserted, if the error indication arrived on the
Interlaken link but the 100G Interlaken IP Core does not detect any of the listed integrity issues in the
incoming packet communication.
The irx_err signal indicates approximately where an error occurs: the corruption could have occurred at
the SOP of the current packet, in some later cycle in the payload of the current packet, in a packet that is
interleaved with the current packet, or in the current EOP cycle. When the IP core identifies an error in
the data it receives on the Interlaken link, it marks every packet currently open on the link as errored,
rather than attempt to associate the error with a specific channel. Therefore, the application need not drop
any packets that are not marked explicitly as errored using one of the two mechanisms.
The irx_err signal asserts one time only, whether a single error or multiple errors occurred in the packet.
If the current EOP cycle data is corrupted so badly that the EOP indication is missing, the irx_err error
indication is aligned to the next EOP. If an error occurs during an IDLE cycle, the irx_err is aligned to
the next EOP.
The application is responsible for discarding packets it receives from the IP core with irx_err asserted
during the EOP cycle, just as it is responsible for discarding packets it receives from the IP core with
irx_eopbits set to 4'b0001. If you turn on Include advanced error reporting and handling, the applica‐
tion is not responsible for tracking the open packets interleaved with the errored packet — the
100G Interlaken IP Core asserts irx_err in the EOP cycle of every potentially errored packet, and the
4-24
100G Interlaken IP Core RX Errored Packet Handling
UG-01128
2015.05.04
Altera Corporation
Functional Description
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About This MegaCore Function 3
- Device Family Support 6
- IP Core Verification 7
- Device Speed Grade Support 9
- Release Information 9
- Altera IP Core Release Notes 10
- OpenCore Plus IP Evaluation 11
- - HDL synthesis file 13
- 10 variation 14
- Pin Assignments 16
- Adding the External PLL 22
- 100G Interlaken IP Core 23
- Number of Lanes 25
- Meta Frame Length in Words 26
- Data Rate 26
- Enable M20K ECC Support 28
- Include Diagnostic Features 28
- Number of Calendar Pages 29
- TX Scrambler Seed 29
- Transfer Mode Selection 30
- Data Format 30
- Functional Description 31
- Management Interface 32
- High Level Block Diagram 34
- IP Core Reset 35
- Interleaved and Packet Modes 37
- Dual Segment Mode 38
- M20K ECC Support 40
- Device Dependent Signals 72
- Offset Name R/W Description 76
- Example Design 82
- Top Testbench 82
- Testbench Simulation Behavior 83
- Simulating the Example Design 84
- Internal Serial Loopback Mode 86
- External Loopback Mode 87
- CRC32 Error Injection 92
- CRC24 Error Injection 93
- Advanced Parameter Settings 94
- RXFIFO Address Width 95
- Subscribe 98
- UG-01128 100
- 2015.05.04 100
- Signal Name Direction Width 102
- Description 102
- Related Information 102
- Ethernet Traffic 103
- Altera Corporation 105
- Send Feedback 105
- Additional Information 106
- Date ACDS 107
- Changes Made 107
- How to Contact Altera 110
- Typographic Conventions 110
- Visual Cue Meaning 111
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