Altera 100G Interlaken MegaCore Function Manual de usuario Pagina 2
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Contents
About This MegaCore Function......................................................................... 1-1
Features......................................................................................................................................................... 1-1
IP Core Supported Combinations of Number of Lanes and Data Rate...................................1-2
IP Core Theoretical Raw Aggregate Bandwidth..........................................................................1-2
Device Family Support................................................................................................................................1-2
IP Core Verification.....................................................................................................................................1-3
Performance and Resource Utilization.....................................................................................................1-3
Device Speed Grade Support......................................................................................................................1-5
Release Information.....................................................................................................................................1-5
Getting Started With the 100G Interlaken IP Core............................................2-1
Installing and Licensing IP Cores..............................................................................................................2-1
OpenCore Plus IP Evaluation........................................................................................................ 2-1
Specifying the 100G Interlaken IP Core Parameters and Options .......................................................2-2
Files Generated for Arria V GZ and Stratix V Variations......................................................................2-3
Files Generated for Arria 10 Variations....................................................................................................2-4
Simulating the100G Interlaken IP Core................................................................................................... 2-6
Integrating Your IP Core in Your Design................................................................................................ 2-6
Pin Assignments...............................................................................................................................2-6
Transceiver Logical Channel Numbering.....................................................................................2-7
Adding the Reconfiguration Controller..................................................................................... 2-10
Adding the External PLL.............................................................................................................. 2-12
Compiling the Full Design and Programming the FPGA....................................................................2-14
100G Interlaken IP Core Parameter Settings.....................................................3-1
Number of Lanes..........................................................................................................................................3-1
Meta Frame Length in Words....................................................................................................................3-2
Data Rate.......................................................................................................................................................3-2
Transceiver Reference Clock Frequency...................................................................................................3-2
Include Advanced Error Reporting and Handling..................................................................................3-3
Enable M20K ECC Support........................................................................................................................3-4
Include Diagnostic Features.......................................................................................................................3-4
Include In-Band Flow Control Block........................................................................................................3-5
Number of Calendar Pages.........................................................................................................................3-5
TX Scrambler Seed.......................................................................................................................................3-5
Transfer Mode Selection.............................................................................................................................3-6
Data Format..................................................................................................................................................3-6
Functional Description....................................................................................... 4-1
Interfaces Overview.....................................................................................................................................4-1
TOC-2
About This MegaCore Function
Altera Corporation
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About This MegaCore Function 3
- Device Family Support 6
- IP Core Verification 7
- Device Speed Grade Support 9
- Release Information 9
- Altera IP Core Release Notes 10
- OpenCore Plus IP Evaluation 11
- - HDL synthesis file 13
- 10 variation 14
- Pin Assignments 16
- Adding the External PLL 22
- 100G Interlaken IP Core 23
- Number of Lanes 25
- Meta Frame Length in Words 26
- Data Rate 26
- Enable M20K ECC Support 28
- Include Diagnostic Features 28
- Number of Calendar Pages 29
- TX Scrambler Seed 29
- Transfer Mode Selection 30
- Data Format 30
- Functional Description 31
- Management Interface 32
- High Level Block Diagram 34
- IP Core Reset 35
- Interleaved and Packet Modes 37
- Dual Segment Mode 38
- M20K ECC Support 40
- Device Dependent Signals 72
- Offset Name R/W Description 76
- Example Design 82
- Top Testbench 82
- Testbench Simulation Behavior 83
- Simulating the Example Design 84
- Internal Serial Loopback Mode 86
- External Loopback Mode 87
- CRC32 Error Injection 92
- CRC24 Error Injection 93
- Advanced Parameter Settings 94
- RXFIFO Address Width 95
- Subscribe 98
- UG-01128 100
- 2015.05.04 100
- Signal Name Direction Width 102
- Description 102
- Related Information 102
- Ethernet Traffic 103
- Altera Corporation 105
- Send Feedback 105
- Additional Information 106
- Date ACDS 107
- Changes Made 107
- How to Contact Altera 110
- Typographic Conventions 110
- Visual Cue Meaning 111
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