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Signal Name Direction Width
(Bits)
Description
irx_
eopbits
Output 4 Indicates whether the current data symbol contains the end of a packet
(EOP) with or without an error, and specifies the number of valid bytes
in the current end-of-packet, non-error 8-byte data word, if relevant.
The IP core sets the value of irx_eopbits as follows:
• 4b’0000: no end of packet, no error.
• 4b’0001: Error and end of packet.
• 4b’1xxx: End of packet. xxx indicates the number of valid bytes in
the final valid 8-byte word of the packet, as follows:
• 3b’000: all 8 bytes are valid.
• 3b’001: 1 byte is valid.
• ...
• 3b’111: 7 bytes are valid.
All other values (4'b01xx, 4'b001x) are undefined and are not generated
by the IP core.
The valid bytes always start in bit positions [63:56] of the final valid
data word of the packet.
irx_sob Output 2 Start of the burst. The 100G Interlaken IP core indicates the start of the
burst. The signal irx_channel is only valid when irx_sob is high. This
signal toggles in Packet Mode and in Interleaved Mode.
This signal has the following valid values:
• 2'b00—The current data symbol does not contain the start of a
burst.
• 2'b10— If irx_sob[1] has the value of 1, the start-of-burst aligns
with the most significant byte (byte 63) of the data.
• 2'b01— If irx_sob[0] has the value of 1, the start-of-burst aligns
with byte 31 of the data.
irx_eob Output 1 End of the burst. The 100G Interlaken IP core indicates the end of the
burst. This signal toggles in Packet Mode and in Interleaved Mode.
irx_dout_
words
Output
512
The eight 64-bit words of output data (one data symbol). When irx_
num_valid has the value of zero, you should ignore irx_dout_words.
irx_
calendar
Output 16 × N Multiple pages (16 bits per page) of calendar output bits. The value is
the in-band flow control bits from N control words on the incoming
Interlaken link. N is the value of the Number of calendar pages
parameter, which can be any of 1, 2, 4, 8, or 16. This signal is synchro‐
nous with rx_usr_clk, although it is not part of the user data transfer
protocol.
5-8
100G Interlaken IP Core User Data Transfer Interface Signals
UG-01128
2015.05.04
Altera Corporation
100G Interlaken MegaCore Function Signals
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About This MegaCore Function 3
- Device Family Support 6
- IP Core Verification 7
- Device Speed Grade Support 9
- Release Information 9
- Altera IP Core Release Notes 10
- OpenCore Plus IP Evaluation 11
- - HDL synthesis file 13
- 10 variation 14
- Pin Assignments 16
- Adding the External PLL 22
- 100G Interlaken IP Core 23
- Number of Lanes 25
- Meta Frame Length in Words 26
- Data Rate 26
- Enable M20K ECC Support 28
- Include Diagnostic Features 28
- Number of Calendar Pages 29
- TX Scrambler Seed 29
- Transfer Mode Selection 30
- Data Format 30
- Functional Description 31
- Management Interface 32
- High Level Block Diagram 34
- IP Core Reset 35
- Interleaved and Packet Modes 37
- Dual Segment Mode 38
- M20K ECC Support 40
- Device Dependent Signals 72
- Offset Name R/W Description 76
- Example Design 82
- Top Testbench 82
- Testbench Simulation Behavior 83
- Simulating the Example Design 84
- Internal Serial Loopback Mode 86
- External Loopback Mode 87
- CRC32 Error Injection 92
- CRC24 Error Injection 93
- Advanced Parameter Settings 94
- RXFIFO Address Width 95
- Subscribe 98
- UG-01128 100
- 2015.05.04 100
- Signal Name Direction Width 102
- Description 102
- Related Information 102
- Ethernet Traffic 103
- Altera Corporation 105
- Send Feedback 105
- Additional Information 106
- Date ACDS 107
- Changes Made 107
- How to Contact Altera 110
- Typographic Conventions 110
- Visual Cue Meaning 111
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