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100G Interlaken IP Core Parameter Settings
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You customize the 100G Interlaken IP core by specifying parameters in the 100G Interlaken parameter
editor, which you access from the Quartus II IP Catalog.
This chapter describes the parameters and how they affect the behavior of the IP core. To customize your
100G Interlaken IP core, you can modify parameters to specify the following properties:
Number of Lanes on page 3-1
Meta Frame Length in Words on page 3-2
Data Rate on page 3-2
Transceiver Reference Clock Frequency on page 3-2
Include Advanced Error Reporting and Handling on page 3-3
Enable M20K ECC Support on page 3-4
Include Diagnostic Features on page 3-4
Include In-Band Flow Control Block on page 3-5
Number of Calendar Pages on page 3-5
TX Scrambler Seed on page 3-5
Transfer Mode Selection on page 3-6
Data Format on page 3-6
Number of Lanes
The Number of lanes parameter specifies the number of lanes available for Interlaken communication.
The supported values are 12 and 24.
The default value of the Number of lanes parameter is 12.
The 100G Interlaken MegaCore function supports various combinations of number of lanes and lane
rates. Ensure that your parameter settings specify a supported combination.
©
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
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101 Innovation Drive, San Jose, CA 95134
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About This MegaCore Function 3
- Device Family Support 6
- IP Core Verification 7
- Device Speed Grade Support 9
- Release Information 9
- Altera IP Core Release Notes 10
- OpenCore Plus IP Evaluation 11
- - HDL synthesis file 13
- 10 variation 14
- Pin Assignments 16
- Adding the External PLL 22
- 100G Interlaken IP Core 23
- Number of Lanes 25
- Meta Frame Length in Words 26
- Data Rate 26
- Enable M20K ECC Support 28
- Include Diagnostic Features 28
- Number of Calendar Pages 29
- TX Scrambler Seed 29
- Transfer Mode Selection 30
- Data Format 30
- Functional Description 31
- Management Interface 32
- High Level Block Diagram 34
- IP Core Reset 35
- Interleaved and Packet Modes 37
- Dual Segment Mode 38
- M20K ECC Support 40
- Device Dependent Signals 72
- Offset Name R/W Description 76
- Example Design 82
- Top Testbench 82
- Testbench Simulation Behavior 83
- Simulating the Example Design 84
- Internal Serial Loopback Mode 86
- External Loopback Mode 87
- CRC32 Error Injection 92
- CRC24 Error Injection 93
- Advanced Parameter Settings 94
- RXFIFO Address Width 95
- Subscribe 98
- UG-01128 100
- 2015.05.04 100
- Signal Name Direction Width 102
- Description 102
- Related Information 102
- Ethernet Traffic 103
- Altera Corporation 105
- Send Feedback 105
- Additional Information 106
- Date ACDS 107
- Changes Made 107
- How to Contact Altera 110
- Typographic Conventions 110
- Visual Cue Meaning 111
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