Altera 100G Interlaken MegaCore Function Manual de usuario Pagina 27
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If the actual frequency of the pll_ref_clk input clock does not match the value you specify for this
parameter, the design fails in both simulation and hardware.
Table 3-3: 100G Interlaken IP Core Supported pll_ref_clk Frequencies
The sets of valid frequencies vary with the per-lane data rate of the transceivers.
Per-Lane Data Rate Valid pll_ref_clk Frequencies (MHz)
10.3125 206.25, 257.8125, 322.265625, 412.5, 515.625, 644.53125
12.5, 6.25 156.25, 195.3125, 250, 312.5, 390.625, 500, 625
The default value of the Transceiver reference clock frequency parameter is 412.5 MHz.
Related Information
• 100G Interlaken IP Core Clock Signals on page 4-5
• 100G Interlaken IP Core Clock Interface Signals on page 5-1
Include Advanced Error Reporting and Handling
The Include advanced error reporting and handling parameter specifies whether your 100G Interlaken
MegaCore function checks the integrity of incoming packets on the Interlaken link and reports the packet
corruption errors it detects.
If you turn on Include advanced error reporting and handling, the IP core reports the following errors
on the irx_err output signal:
• CRC24 errors
• Loss of lane alignment
• Illegal control word
• Illegal framing pattern
• Missing SOP or EOP indicator
If you turn off Include advanced error reporting and handling, the irx_err signal acts identically to the
crc24_err signal: it reports only CRC24 errors.
Your IP core calculates and inserts CRC24 bits in outgoing Interlaken communication, and checks
incoming Interlaken communication for CRC24 errors in the control and data words, whether or not you
turn on this parameter.
If you turn this parameter on, your IP core reports incoming packet corruption errors, increasing system
robustness. If you turn the parameter off your IP core has lower latency and requires fewer resources on
the device.
A checkmark in the check box to the left of the parameter turns this parameter on, specifying that the IP
core include this feature. A check box with no checkmark indicates that the option is turned off, and the
IP core does not include the feature.
By default, the Include advanced error reporting and handling parameter is turned off.
Related Information
100G Interlaken IP Core RX Errored Packet Handling on page 4-24
UG-01128
2015.05.04
Include Advanced Error Reporting and Handling
3-3
100G Interlaken IP Core Parameter Settings
Altera Corporation
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- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About This MegaCore Function 3
- Device Family Support 6
- IP Core Verification 7
- Device Speed Grade Support 9
- Release Information 9
- Altera IP Core Release Notes 10
- OpenCore Plus IP Evaluation 11
- - HDL synthesis file 13
- 10 variation 14
- Pin Assignments 16
- Adding the External PLL 22
- 100G Interlaken IP Core 23
- Number of Lanes 25
- Meta Frame Length in Words 26
- Data Rate 26
- Enable M20K ECC Support 28
- Include Diagnostic Features 28
- Number of Calendar Pages 29
- TX Scrambler Seed 29
- Transfer Mode Selection 30
- Data Format 30
- Functional Description 31
- Management Interface 32
- High Level Block Diagram 34
- IP Core Reset 35
- Interleaved and Packet Modes 37
- Dual Segment Mode 38
- M20K ECC Support 40
- Device Dependent Signals 72
- Offset Name R/W Description 76
- Example Design 82
- Top Testbench 82
- Testbench Simulation Behavior 83
- Simulating the Example Design 84
- Internal Serial Loopback Mode 86
- External Loopback Mode 87
- CRC32 Error Injection 92
- CRC24 Error Injection 93
- Advanced Parameter Settings 94
- RXFIFO Address Width 95
- Subscribe 98
- UG-01128 100
- 2015.05.04 100
- Signal Name Direction Width 102
- Description 102
- Related Information 102
- Ethernet Traffic 103
- Altera Corporation 105
- Send Feedback 105
- Additional Information 106
- Date ACDS 107
- Changes Made 107
- How to Contact Altera 110
- Typographic Conventions 110
- Visual Cue Meaning 111
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