Altera 100G Interlaken MegaCore Function Manual de usuario Pagina 64
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Signal Name Direction Width
(Bits)
Description
itx_
calendar
Input 16 N Multiple pages (16 bits per page) of calendar input bits. The
100G Interlaken IP Core copies these bits to the in-band flow control
bits in N control words that it sends on the Interlaken link. N is the
value of the Number of calendar pages parameter, which can be any of
1, 2, 4, 8. or 16. This signal is synchronous with tx_usr_clk, although
it is not part of the user data transfer protocol.
itx_ready Output 1 Flow control signal to back pressure transmit traffic. When this signal
is high, you can send traffic to the IP core. When this signal is low, you
should stop sending traffic to the IP core within one to four cycles.
You can consider the inverse of itx_ready to be a FIFO-almost-full
indicator. In full duplex mode, itx_ready is low when rx_lanes_
aligned is low.
itx_ifc_
err
Output 1
Indicates the transmit side user data transfer interface received traffic
that the 100G Interlaken IP Core does not support. The IP core asserts
the itx_ifc_err signal in the following cases:
• In Interleaved mode, the IP core receives a burst that exceeds the
size of MaxBurst.
• itx_sop or itx_sob has the invalid value of 2'b11 in a valid data
cycle.
• Two instances of non-zero itx_sop (a start of packet), or two
instances of non-zero itx_sob (a start of burst), are separated by
fewer than 64 bytes.
The IP core asserts the itx_ifc_err signal for a single clock cycle. The
signal pulses within the current burst, with a delay of one or two cycles
after the error on the transmit side user data transfer interface.
100G Interlaken IP Core Receive User Interface
irx_chan Output 8 Receive logic channel number. The IP core supports up to 256
channels. You should sample this value when a bit of irx_sop or irx_
sob is high and irx_num_valid has a non-zero value.
5-6
100G Interlaken IP Core User Data Transfer Interface Signals
UG-01128
2015.05.04
Altera Corporation
100G Interlaken MegaCore Function Signals
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About This MegaCore Function 3
- Device Family Support 6
- IP Core Verification 7
- Device Speed Grade Support 9
- Release Information 9
- Altera IP Core Release Notes 10
- OpenCore Plus IP Evaluation 11
- - HDL synthesis file 13
- 10 variation 14
- Pin Assignments 16
- Adding the External PLL 22
- 100G Interlaken IP Core 23
- Number of Lanes 25
- Meta Frame Length in Words 26
- Data Rate 26
- Enable M20K ECC Support 28
- Include Diagnostic Features 28
- Number of Calendar Pages 29
- TX Scrambler Seed 29
- Transfer Mode Selection 30
- Data Format 30
- Functional Description 31
- Management Interface 32
- High Level Block Diagram 34
- IP Core Reset 35
- Interleaved and Packet Modes 37
- Dual Segment Mode 38
- M20K ECC Support 40
- Device Dependent Signals 72
- Offset Name R/W Description 76
- Example Design 82
- Top Testbench 82
- Testbench Simulation Behavior 83
- Simulating the Example Design 84
- Internal Serial Loopback Mode 86
- External Loopback Mode 87
- CRC32 Error Injection 92
- CRC24 Error Injection 93
- Advanced Parameter Settings 94
- RXFIFO Address Width 95
- Subscribe 98
- UG-01128 100
- 2015.05.04 100
- Signal Name Direction Width 102
- Description 102
- Related Information 102
- Ethernet Traffic 103
- Altera Corporation 105
- Send Feedback 105
- Additional Information 106
- Date ACDS 107
- Changes Made 107
- How to Contact Altera 110
- Typographic Conventions 110
- Visual Cue Meaning 111
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