Altera Stratix V Avalon-ST Manual de usuario Pagina 73
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Signal Direction Description
• 5’b10011: Loopback.Exit
• 5’b10100: Hot.Reset
• 5’b10101: L0s
• 5’b11001: L2.transmit.Wake
• 5’b11010: Speed.Recovery
• 5’b11011: Recovery.Equalization, Phase 0
• 5’b11100: Recovery.Equalization, Phase 1
• 5’b11101: Recovery.Equalization, Phase 2
• 5’b11110: Recovery.Equalization, Phase 3
• 5’b11111: Recovery.Equalization, Done
sim_pipe_pclk_in
Input This clock is used for PIPE simulation only, and is derived from
the refclk. It is the PIPE interface clock used for PIPE mode
simulation.
sim_pipe_rate[1:0]
Input Specifies the data rate. The 2-bit encodings have the following
meanings:
• 2’b00: Gen1 rate (2.5 Gbps)
• 2’b01: Gen2 rate (5.0 Gbps)
• 2’b1X: Gen3 rate (8.0 Gbps)
txcompl0 Output Transmit compliance <n>. This signal forces the running
disparity to negative in compliance mode (negative COM
character).
txdata0[31:0]
Output Transmit data. This bus transmits data on lane <n>.
txdatak0[3:0]
Output Transmit data control <n>. This signal serves as the control bit
for txdata <n>. Bit 0 corresponds to the lowest-order byte of
rxdata, and so on. A value of 0 indicates a data byte. A value of 1
indicates a control byte. For Gen1 and Gen2 only.
txdataskip0
Output For Gen3 operation. Allows the MAC to instruct the TX interface
to ignore the TX data interface for one clock cycle. The following
encodings are defined:
• 1’b0: TX data is invalid
• 1’b1: TX data is valid
txdeemph0
Output Transmit de-emphasis selection. The value for this signal is set
based on the indication received from the other end of the link
during the Training Sequences (TS). You do not need to change
this value.
4-38
PIPE Interface Signals
UG-01097_sriov
2014.12.15
Altera Corporation
Interfaces and Signal Descriptions
Send Feedback
- User Guide 1
- Datasheet 2
- Features 3
- Interface 4
- Release Information 7
- Device Family Support 7
- Example Designs 8
- Debug Features 8
- IP Core Verification 9
- Recommended Speed Grades 10
- Related Information 11
- Subscribe 12
- Qsys Subsystem Description 13
- Parameter Value 15
- Directory Description 16
- Parameter Settings 21
- Parameter Value Description 22
- SR-IOV System Settings 24
- Interrupt Capabilities 27
- Device Capabilities 29
- Error Reporting 30
- Link Capabilities 31
- Slot Capabilities 32
- Power Management 33
- PHY Characteristics 34
- Simulation Options 35
- Avalon-ST TX Interface 37
- Signal Direction Description 38
- Avalon‑ST RX Interface 40
- BAR Hit Signals 43
- Completion Side Band Signals 45
- Signal Directi 46
- Description 46
- Clock Signals 48
- Interrupt Interface 49
- Implementing MSI-X Interrupts 55
- LMI Signals 57
- Serial Data Signals 65
- Test Signals 70
- PIPE Interface Signals 71
- Byte Address 77
- MSI Registers 80
- MSI-X Capability Structure 82
- VF Device ID Register 96
- Page Size Registers 96
- Lane Error Status Register 98
- Bits Register Description 99
- Default Value 99
- Altera Corporation 100
- Registers 100
- Send Feedback 100
- Virtual Function Registers 102
- Name Description 103
- Reset and Clocks 107
- Hard IP for PCI Express 108
- Example Design 108
- UG-01097_sriov 109
- 2014.12.15 109
- Function Level Reset (FLR) 111
- Clock Domains 111
- Clock Summary 114
- Interrupts 115
- Error Handling 118
- Physical Layer Errors 119
- Data Link Layer Errors 119
- Transaction Layer Errors 120
- Error Type Description 121
- Status Bit Conditions 123
- IP Core Architecture 125
- Top-Level Interfaces 126
- Clocks and Reset 126
- Transceiver Reconfiguration 126
- Data Link Layer 127
- Physical Layer 129
- TX Packets 130
- Design Implementation 136
- CONF_DONE 137
- Endpoint Reset 137
- Root Port Reset 137
- SDC Timing Constraints 138
- Debugging 143
- Setting Up Simulation 146
- Use Third-Party PCIe Analyzer 148
- BIOS Enumeration Issues 148
- Address[31:2] 149
- Figure A-6: I/O Read Request 151
- Additional Information 155
- Typographic Conventions 156
- Visual Cue Meaning 157
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