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Altera Stratix V Avalon-ST manuales

Manuales del propietario y guías del usuario para Instrumentos de medición Altera Stratix V Avalon-ST.
Ofrecemos 2 manuales en pdf Altera Stratix V Avalon-ST para descargar gratis por tipos de documentos: Manual de usuario


Altera Stratix V Avalon-ST Manual de usuario (158 paginas)


Marca: Altera | Categoria: Instrumentos de medición | Tamaño: 1.58 MB |

 

Tabla de contenidos

User Guide

1

Datasheet

2

Features

3

Interface

4

Release Information

7

Device Family Support

7

Example Designs

8

Debug Features

8

IP Core Verification

9

Recommended Speed Grades

10

Related Information

11

Subscribe

12

Qsys Subsystem Description

13

Parameter Value

15

Directory Description

16

Parameter Settings

21

Parameter Value Description

22

SR-IOV System Settings

24

Interrupt Capabilities

27

Device Capabilities

29

Error Reporting

30

Link Capabilities

31

Slot Capabilities

32

Power Management

33

PHY Characteristics

34

Simulation Options

35

Avalon-ST TX Interface

37

Signal Direction Description

38

Avalon‑ST RX Interface

40

BAR Hit Signals

43

Completion Side Band Signals

45

Signal Directi

46

Description

46

Clock Signals

48

Interrupt Interface

49

Implementing MSI-X Interrupts

55

LMI Signals

57

Serial Data Signals

65

Test Signals

70

PIPE Interface Signals

71

Byte Address

77

MSI Registers

80

MSI-X Capability Structure

82

VF Device ID Register

96

Page Size Registers

96

Lane Error Status Register

98

Bits Register Description

99

Default Value

99

Altera Corporation

100

Registers

100

Send Feedback

100

Virtual Function Registers

102

Name Description

103

Reset and Clocks

107

Hard IP for PCI Express

108

Example Design

108

UG-01097_sriov

109

2014.12.15

109

Function Level Reset (FLR)

111

Clock Domains

111

Clock Summary

114

Interrupts

115

Error Handling

118

Physical Layer Errors

119

Data Link Layer Errors

119

Transaction Layer Errors

120

Error Type Description

121

Status Bit Conditions

123

IP Core Architecture

125

Top-Level Interfaces

126

Clocks and Reset

126

Transceiver Reconfiguration

126

Data Link Layer

127

Physical Layer

129

TX Packets

130

Design Implementation

136

CONF_DONE

137

Endpoint Reset

137

Root Port Reset

137

SDC Timing Constraints

138

Debugging

143

Setting Up Simulation

146

Use Third-Party PCIe Analyzer

148

BIOS Enumeration Issues

148

Address[31:2]

149

Figure A-6: I/O Read Request

151

Additional Information

155

Typographic Conventions

156

Visual Cue Meaning

157

Altera Stratix V Avalon-ST Manual de usuario (293 paginas)


Marca: Altera | Categoria: Instrumentos de medición | Tamaño: 2.34 MB |

 

Tabla de contenidos

User Guide

1

Datasheet

2

Features

3

Interface

4

Release Information

7

Device Family Support

7

UG-01097_avst

10

2014.12.15

10

Debug Features

11

IP Core Verification

11

Recommended Speed Grades

12

• All Development Kits

14

PCI Express

15

Qsys Design Flow

16

Generating the Testbench

17

Simulating the Example Design

18

Directory Description

19

Time TLP Type Payload

19

TLP Header

19

Modifying the Example Design

23

Separate Component

24

Generating the Qsys System

27

Parameter Value

28

Parameter Settings

38

Parameter Value Description

39

Device Capabilities

45

Error Reporting

47

Link Capabilities

48

MSI and MSI-X Capabilities

49

Slot Capabilities

50

Power Management

51

PHY Characteristics

52

Avalon‑ST RX Interface

54

Packet TLP

59

Aligned Addresses

64

Single Packet Per Cycle

67

Avalon-ST TX Interface

70

Data 0 Header 2

83

Clock Signals

85

ECRC Forwarding

90

Error Signals

90

Interrupts for Endpoints

91

Completion Side Band Signals

93

Signal Directi

94

Description

94

Related Information

101

Parity Signals

102

LMI Signals

103

Signal Direction Description

104

Altera Corporation

107

Send Feedback

107

Field and Bit Map

112

0134678951

112

Bit(s) Field Description

113

Power Management Signals

115

15 011623 8 2791213142431

117

Transceiver Reconfiguration

118

Serial Data Signals

119

PIPE Interface Signals

123

Test Signals

128

Registers

129

Altera-Defined VSEC Registers

137

CvP Registers

138

2014.08.18

139

Bits Register Description

142

Reset and Clocks

145

Example Design

146

Hard IP for PCI Express

146

Clock Domains

149

Data Rate Frequency

150

Clock Summary

152

Interrupts

153

MSI Interrupts

154

Allocated

155

Implementing MSI-X Interrupts

156

Legacy Interrupts

158

Interrupts for Root Ports

159

Error Handling

160

Physical Layer Errors

161

Data Link Layer Errors

161

Transaction Layer Errors

162

Error Type Description

163

Status Bit Conditions

166

IP Core Architecture

168

Hard IP for PCI Express

169

Top-Level Interfaces

170

Avalon-ST Interface

170

Clocks and Reset

171

Hard IP Reconfiguration

171

Transaction Layer

172

Configuration Space

173

(Soft Logic)

175

Altera FPGA

175

Protocol Extensions Supported

179

Data Link Layer

179

Physical Layer

181

TX Packets

182

Supported Message Types

184

INTX Messages

184

Power Management Messages

185

Error Signaling Messages

186

Locked Transaction Message

187

Slot Power Limit Message

187

Vendor-Defined Messages

187

Hot Plug Messages

188

Receive Buffer Reordering

190

Using Relaxed Ordering

192

Throughput Optimization

195

Throughput of Posted Writes

197

Design Implementation

199

CONF_DONE

200

Endpoint Reset

200

Root Port Reset

200

SDC Timing Constraints

201

Optional Features

203

ECRC on the RX Path

204

ECRC on the TX Path

205

Subscribe

208

Testbench and Design Example

212

Root Port Testbench

215

Chaining DMA Design Examples

215

Root Complex

217

Chaining DMA

217

Hard IP for

217

BAR/Address Map

220

Memory BAR Mapping

221

Bit Field Description

222

Addr Register Name

222

Byte Address

225

Offset to Base

225

Descriptor Type Description

225

Bits[21:18] Bit[17] Bit[16]

226

Descriptor Field Endpoint

226

RC Access Description

226

Test Driver Module

227

DMA Write Cycles

228

Shared Memory

229

DMA Read Cycles

230

Registers (BAR2)

231

Root Port Design Example

232

Root Port

233

Variation

233

(variation_name.v)

233

Root Port BFM

234

BFM Configuration Procedures

235

BFM Request Interface

235

BFM Memory Map

236

Offset (Bytes) Description

238

BFM Procedures and Functions

242

Location altpcietb_bfm_rdwr.v

243

Express address

244

Shared Memory Constants

251

Constant Description

252

Location

257

Debugging Simulations

269

Debugging

270

Setting Up Simulation

276

Use Third-Party PCIe Analyzer

277

BIOS Enumeration Issues

277

Address[31:2]

278

Figure A-6: I/O Read Request

280

7 6 5 4 3 2 1 0

284

Core Config 8 4 1

284

Additional Information

286

Date Version Changes Made

287

How to Contact Altera

290

Typographic Conventions

291

Visual Cue Meaning

292




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