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Table 1-1: PCI Express Data Throughput
The following table shows the aggregate bandwidth of a PCI Express link for Gen1, Gen2, and Gen3 for supported
link widths. The protocol specifies 2.5 giga-transfers per second for Gen1, 5.0 giga-transfers per second for Gen2,
and 8.0 giga-transfers per second for Gen3. This table provides bandwidths for a single transmit (TX) or receive
(RX) channel. The numbers double for duplex operation. Gen1 and Gen2 use 8B/10B encoding which introduces
a 20% overhead. In contrast, Gen3 uses 128b/130b encoding which reduces the data throughput lost to encoding
to less than 1%.
Link Width
×2 ×4 ×8
PCI Express Gen1 (2.5 Gbps) - 128-bit interface
N/A N/A
16
PCI Express Gen2 (5.0 Gbps) - 128-bit interface
N/A
16 32
PCI Express Gen2 (5.0 Gbps) - 256-bit interface
N/A N/A
32
PCI Express Gen3 (8.0 Gbps) - 128-bit interface 15.75 31.51
N/A
PCI Express Gen3 (8.0 Gbps) - 256-bit interface
N/A N/A
63
Related Information
• PCI Express Base Specification 2.1 or 3.0
• Single Root I/O Virtualization and Sharing Specification Revision 1.1.
• Stratix V Avalon-ST Interface for PCIe Solutions User Guide
• Creating a System with Qsys
Features
New features in the Quartus
®
II 14.1 software release:
• Reduced Quartus II compilation warnings by 50%.
The Stratix V Hard IP for PCI Express with SR-IOV supports the following features:
• Complete protocol stack including the Transaction, Data Link, and Physical Layers implemented as
hard IP.
• Support for ×2, ×4, and ×8 configurations with Gen1, Gen2, or Gen3 lane rates for Endpoints.
Downtrains to appropriate configuration when plugged into a lower bandwidth configuration,
including Gen1 x1, Gen1 x2, and so on.
• Dedicated 16 KByte receive buffer.
• Optional hard reset controller for Gen2.
• Qsys example designs demonstrating parameterization, design modules, and connectivity.
• Extended credit allocation settings to better optimize the RX buffer space based on application type.
• End-to-end cyclic redundancy code (ECRC) generation and checking and advanced error reporting
(AER) for high reliability applications.
1-2
Features
UG-01097_sriov
2014.12.15
Altera Corporation
Datasheet
Send Feedback
- User Guide 1
- Datasheet 2
- Features 3
- Interface 4
- Release Information 7
- Device Family Support 7
- Example Designs 8
- Debug Features 8
- IP Core Verification 9
- Recommended Speed Grades 10
- Related Information 11
- Subscribe 12
- Qsys Subsystem Description 13
- Parameter Value 15
- Directory Description 16
- Parameter Settings 21
- Parameter Value Description 22
- SR-IOV System Settings 24
- Interrupt Capabilities 27
- Device Capabilities 29
- Error Reporting 30
- Link Capabilities 31
- Slot Capabilities 32
- Power Management 33
- PHY Characteristics 34
- Simulation Options 35
- Avalon-ST TX Interface 37
- Signal Direction Description 38
- Avalon‑ST RX Interface 40
- BAR Hit Signals 43
- Completion Side Band Signals 45
- Signal Directi 46
- Description 46
- Clock Signals 48
- Interrupt Interface 49
- Implementing MSI-X Interrupts 55
- LMI Signals 57
- Serial Data Signals 65
- Test Signals 70
- PIPE Interface Signals 71
- Byte Address 77
- MSI Registers 80
- MSI-X Capability Structure 82
- VF Device ID Register 96
- Page Size Registers 96
- Lane Error Status Register 98
- Bits Register Description 99
- Default Value 99
- Altera Corporation 100
- Registers 100
- Send Feedback 100
- Virtual Function Registers 102
- Name Description 103
- Reset and Clocks 107
- Hard IP for PCI Express 108
- Example Design 108
- UG-01097_sriov 109
- 2014.12.15 109
- Function Level Reset (FLR) 111
- Clock Domains 111
- Clock Summary 114
- Interrupts 115
- Error Handling 118
- Physical Layer Errors 119
- Data Link Layer Errors 119
- Transaction Layer Errors 120
- Error Type Description 121
- Status Bit Conditions 123
- IP Core Architecture 125
- Top-Level Interfaces 126
- Clocks and Reset 126
- Transceiver Reconfiguration 126
- Data Link Layer 127
- Physical Layer 129
- TX Packets 130
- Design Implementation 136
- CONF_DONE 137
- Endpoint Reset 137
- Root Port Reset 137
- SDC Timing Constraints 138
- Debugging 143
- Setting Up Simulation 146
- Use Third-Party PCIe Analyzer 148
- BIOS Enumeration Issues 148
- Address[31:2] 149
- Figure A-6: I/O Read Request 151
- Additional Information 155
- Typographic Conventions 156
- Visual Cue Meaning 157
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