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For descriptions of the available reset signals, refer to Reset Signals, Status, and Link Training Signals.
Function Level Reset (FLR)
The following sequence of events occurs after a FLR to a Physical Function:
1. The host stops all traffic from and to the Function.
2. The host writes the FLR bit in the Device Control Register to trigger the FLR reset.
3. The SR-IOV Bridge resets R/W non-sticky control bits in the Configuration Space of the Function. It
notifies the Application Layer via flr_active_* signals.
4. The Application Layer cleans up all state related to the Function. It asserts FLR Completed via
flr_completed_* signal. The Application Layer should either discard all pending requests from the
Function, or send Completions. If the Application Layer sends Completions, the host drops them
without checking for errors.
5. The SR-IOV Bridge re-enables the Function by deasserting the flr_active_* signal associated with
this function.
6. The host re-enumerates the Function.
This handshake ensures that the Completion for a request issued before the FLR does not return
after the FLR is complete.
Related Information
Function-Level Reset Interface on page 4-13
Clocks
The Hard IP contains a clock domain crossing (CDC) synchronizer at the interface between the
PHY/MAC and the DLL layers. The synchronizer allows the Data Link and Transaction Layers to run at
frequencies independent of the PHY/MAC. The CDC synchronizer provides more flexibility for the user
clock interface. Depending on parameters you specify, the core selects the appropriate coreclkout_hip.
You can use these parameters to enhance performance by running at a higher frequency for latency
optimization or at a lower frequency to save power.
In accordance with the PCI Express Base Specification, you must provide a 100 MHz reference clock that is
connected directly to the transceiver.
As a convenience, you may also use a 125 MHz input reference clock as input to the TX PLL.
Related Information
PCI Express Base Specification 2.1 or 3.0
Clock Domains
UG-01097_sriov
2014.12.15
Function Level Reset (FLR)
6-5
Reset and Clocks
Altera Corporation
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- User Guide 1
- Datasheet 2
- Features 3
- Interface 4
- Release Information 7
- Device Family Support 7
- Example Designs 8
- Debug Features 8
- IP Core Verification 9
- Recommended Speed Grades 10
- Related Information 11
- Subscribe 12
- Qsys Subsystem Description 13
- Parameter Value 15
- Directory Description 16
- Parameter Settings 21
- Parameter Value Description 22
- SR-IOV System Settings 24
- Interrupt Capabilities 27
- Device Capabilities 29
- Error Reporting 30
- Link Capabilities 31
- Slot Capabilities 32
- Power Management 33
- PHY Characteristics 34
- Simulation Options 35
- Avalon-ST TX Interface 37
- Signal Direction Description 38
- Avalon‑ST RX Interface 40
- BAR Hit Signals 43
- Completion Side Band Signals 45
- Signal Directi 46
- Description 46
- Clock Signals 48
- Interrupt Interface 49
- Implementing MSI-X Interrupts 55
- LMI Signals 57
- Serial Data Signals 65
- Test Signals 70
- PIPE Interface Signals 71
- Byte Address 77
- MSI Registers 80
- MSI-X Capability Structure 82
- VF Device ID Register 96
- Page Size Registers 96
- Lane Error Status Register 98
- Bits Register Description 99
- Default Value 99
- Altera Corporation 100
- Registers 100
- Send Feedback 100
- Virtual Function Registers 102
- Name Description 103
- Reset and Clocks 107
- Hard IP for PCI Express 108
- Example Design 108
- UG-01097_sriov 109
- 2014.12.15 109
- Function Level Reset (FLR) 111
- Clock Domains 111
- Clock Summary 114
- Interrupts 115
- Error Handling 118
- Physical Layer Errors 119
- Data Link Layer Errors 119
- Transaction Layer Errors 120
- Error Type Description 121
- Status Bit Conditions 123
- IP Core Architecture 125
- Top-Level Interfaces 126
- Clocks and Reset 126
- Transceiver Reconfiguration 126
- Data Link Layer 127
- Physical Layer 129
- TX Packets 130
- Design Implementation 136
- CONF_DONE 137
- Endpoint Reset 137
- Root Port Reset 137
- SDC Timing Constraints 138
- Debugging 143
- Setting Up Simulation 146
- Use Third-Party PCIe Analyzer 148
- BIOS Enumeration Issues 148
- Address[31:2] 149
- Figure A-6: I/O Read Request 151
- Additional Information 155
- Typographic Conventions 156
- Visual Cue Meaning 157
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