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Table 4-16: Number of Logical and Physical Reconfiguration Interfaces
Variant Logical Interfaces
Gen2 ×4 5
Gen1 and Gen2 ×8 10
Gen3 ×4 6
Gen3 ×8 11
For more information about the Transceiver Reconfiguration Controller, refer to the Transceiver Reconfi‐
guration Controller chapter in the Altera Transceiver PHY IP Core User Guide .
Related Information
Altera Transceiver PHY IP Core User Guide
Serial Data Signals
Table 4-17: 1-Bit Interface Signals
Signal Direction Description
tx_out[7:0]
(1)
Output Transmit output. These signals are the serial outputs of lanes 7–0.
rx_in[7:0]
(1)
Input Receive input. These signals are the serial inputs of lanes 7–0.
Note:
1. The x1 IP core only has lane 0. The x2 IP core only has lanes 1–0. The x4 IP core only has lanes 3–0.
Refer to Pin-out Files for Altera Devices for pin-out tables for all Altera devices in .pdf, .txt, and .xls
formats.
Transceiver channels are arranged in groups of six. For GX devices, the lowest six channels on the left side
of the device are labeled GXB_L0, the next group is GXB_L1, and so on. Channels on the right side of the
device are labeled GXB_R0, GXB_R1, and so on. Be sure to connect the Hard IP for PCI Express on the
left side of the device to appropriate channels on the left side of the device, as specified in the Pin-out Files
for Altera Devices.
Related Information
Pin-out Files for Altera Devices
Physical Layout of Hard IP In Stratix V Devices
Stratix V devices include one, two, or four Hard IP for PCI Express IP cores. The following figures
illustrate the placement of the PCIe IP cores, transceiver banks, and channels for the largest Stratix V
4-30
Serial Data Signals
UG-01097_sriov
2014.12.15
Altera Corporation
Interfaces and Signal Descriptions
Send Feedback
- User Guide 1
- Datasheet 2
- Features 3
- Interface 4
- Release Information 7
- Device Family Support 7
- Example Designs 8
- Debug Features 8
- IP Core Verification 9
- Recommended Speed Grades 10
- Related Information 11
- Subscribe 12
- Qsys Subsystem Description 13
- Parameter Value 15
- Directory Description 16
- Parameter Settings 21
- Parameter Value Description 22
- SR-IOV System Settings 24
- Interrupt Capabilities 27
- Device Capabilities 29
- Error Reporting 30
- Link Capabilities 31
- Slot Capabilities 32
- Power Management 33
- PHY Characteristics 34
- Simulation Options 35
- Avalon-ST TX Interface 37
- Signal Direction Description 38
- Avalon‑ST RX Interface 40
- BAR Hit Signals 43
- Completion Side Band Signals 45
- Signal Directi 46
- Description 46
- Clock Signals 48
- Interrupt Interface 49
- Implementing MSI-X Interrupts 55
- LMI Signals 57
- Serial Data Signals 65
- Test Signals 70
- PIPE Interface Signals 71
- Byte Address 77
- MSI Registers 80
- MSI-X Capability Structure 82
- VF Device ID Register 96
- Page Size Registers 96
- Lane Error Status Register 98
- Bits Register Description 99
- Default Value 99
- Altera Corporation 100
- Registers 100
- Send Feedback 100
- Virtual Function Registers 102
- Name Description 103
- Reset and Clocks 107
- Hard IP for PCI Express 108
- Example Design 108
- UG-01097_sriov 109
- 2014.12.15 109
- Function Level Reset (FLR) 111
- Clock Domains 111
- Clock Summary 114
- Interrupts 115
- Error Handling 118
- Physical Layer Errors 119
- Data Link Layer Errors 119
- Transaction Layer Errors 120
- Error Type Description 121
- Status Bit Conditions 123
- IP Core Architecture 125
- Top-Level Interfaces 126
- Clocks and Reset 126
- Transceiver Reconfiguration 126
- Data Link Layer 127
- Physical Layer 129
- TX Packets 130
- Design Implementation 136
- CONF_DONE 137
- Endpoint Reset 137
- Root Port Reset 137
- SDC Timing Constraints 138
- Debugging 143
- Setting Up Simulation 146
- Use Third-Party PCIe Analyzer 148
- BIOS Enumeration Issues 148
- Address[31:2] 149
- Figure A-6: I/O Read Request 151
- Additional Information 155
- Typographic Conventions 156
- Visual Cue Meaning 157
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