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The dout_payload signal marks words that contain frame data payload. Words that contain data payload
might also contain Idle or sequence control information, or preamble/frame delimiters. However, if the
word contains any frame data, the dout_payload bit that corresponds to that word has the value of 1.
The dout_valid signal exists for clock rate compensation. This signal is almost always asserted. When
dout_valid is deasserted all other dout signals should be ignored for one clock cycle.
Example on RX Client Interface With Preamble Pass-Through
Figure 3-27: Typical Traffic on the RX Client Interface for 100GbE IP Core Without Adapters and With
Preamble Pass-Through
070707070707070...363738393a3b3c3...5e5f606162636465... 555555555555555D20...8788898a8b8c8d8...afb0b1b2b3b4b5b6... 555555070707070707070...
000007ffff
ffffffff80
ffffffffff
000000001f
0000000000 00000000008000000000
800
10
1000 00
0000800000 0000000200 00000000000000000000
00
00
1f 1c 00 1f 1e 00 1f
00
2
3 5
6
7
81
4
/e100_tb/dut/dout_d
/e100_tb/dut/dout_c
/e100_tb/dut/dout_first_data
/e100_tb/dut/dout_last_data
/e100_tb/dut/dout_runt_last_data
/e100_tb/dut/dout_payload
/e100_tb/dut/dout_fcs_error
/e100_tb/dut/dout_fcs_valid
/e100_tb/dut/dout_dst_addr_match
/e100_tb/dut/dout_valid
/e100_tb/dut/clk_rxmac
In the figure, the IP core is in preamble pass-through mode, and places the preamble sequence on the data
bus dout_d. The dout_first_data signal marks the first word of data, including the full preamble
sequence, beginning with the Start byte. The data in each packet begins with the Start byte (0x55), six-byte
preamble (0x555555555555), and SFD (0xD5), and must align with one of the legal starting positions. The
IP core asserts the dout_c signal high for the Start byte, and holds dout_c low for the remainder of the
preamble, which is considered to be data. The dout_c signal is the only signal that distinguishes any part
of the preamble sequence from data. The second and third packets in the example each begin in the first
word of dout_d, with the preamble sequence. However, they could each legally begin at the start of any
other word of dout_d; the start of each word is a legal starting position.
UG-01088
2014.12.15
100GbE IP Core RX Client Interface Examples
3-31
Functional Description
Altera Corporation
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- MegaCore Function User Guide 1
- Contents 2
- PHY MegaCore Function 4
- 40- or 100-GbE MAC 5
- Device Family Support 7
- IP Core Verification 9
- Simulation Environment 10
- Hardware Testing 10
- Module ALMs Logic Registers 11
- Release Information 21
- Item Description 22
- Getting Started 23
- OpenCore Plus IP Evaluation 24
- IP Core Parameters 25
- Parameter Type Range Default 28
- Parameter Description 28
- Simulating the IP Core 32
- Pin Assignments 33
- 40-100GbE IP Core Testbenches 36
- Testbenches with Adapters 37
- File Names Description 38
- Testbenches without Adapters 40
- Initializing the IP Core 46
- High Level System Overview 49
- 40-100GbE IP Core TX Datapath 50
- Address Insertion 51
- Length/Type Field Processing 52
- Frame Padding 52
- Client Interface 53
- Data Bus Width (Bits) 53
- 40GbE IP Core 100GbE IP Core 53
- 40-100GbE IP Core RX Datapath 67
- RX CRC Forwarding 69
- Address Checking 71
- Inter‑Packet Gap 71
- Pause Ignore 71
- Name Direction Description 73
- 100GbE CAUI–4 PHY 79
- Pause Transmission Logic 82
- Statistics Counters Interface 86
- Name Signal 87
- Direction 87
- Description 87
- Control Data Description 89
- Lane to Lane Deskew Interface 90
- MII Control 91
- MII Data 91
- PCS BER Monitor 92
- Control and Status Interface 98
- Signal Name Description 100
- UG-01088 101
- 2014.12.15 101
- Related Information 102
- Send Feedback 103
- Altera Corporation 103
- Functional Description 103
- Software Interface: Registers 123
- Register Description 124
- 40-100GbE IP Core Registers 126
- Address Name Applicable 128
- Device(s) 128
- Bit Description HW Reset 128
- Bits Description HW Reset 130
- Lock Status Registers 131
- Bit Error Flag Registers 133
- PCS Hardware Error Register 134
- BER Monitor Register 134
- Test Mode Register 135
- Test Pattern Counter Register 135
- MAC and PHY Reset Registers 136
- PCS‑VLANE Registers 138
- PRBS Registers 139
- 40GBASE-KR4 Registers 139
- Pause Registers 149
- MAC Hardware Error Register 151
- CRC Configuration Register 152
- MAC Address Registers 154
- Statistics Registers 155
- PMD Registers 163
- MDIO Registers 164
- Ethernet Glossary 166
- Term Definition 167
- Subscribe 169
- Core v12.0 Release 173
- 10GBASE-KR Registers 174
- Bit R/W Name Description 175
- Additional Information 190
- Date ACDS 191
- at offset 0x127), described 193
- How to Contact Altera 198
- Typographic Conventions 198
- Visual Cue Meaning 199
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