Altera 40-Gbps Ethernet MAC and PHY MegaCore Function Manual de usuario Pagina 55
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Signal Name Direction Description
l<n>_tx_ready
Output When asserted, the MAC is ready to receive data. The
l<n>_tx_ready signal acts as an acknowledge. The source
drives l<n>_tx_valid and l<n>_tx_data[<n>*64-1:0],
then waits for the sink to assert l<n>_tx_ready. The
readyLatency is zero cycles, so that the IP core accepts
valid data in the same cycle in which it asserts l<n>_tx_
ready.
The tx_ready signal indicates the MAC is ready to receive
data in normal operational model. However, the tx_ready
signal might not be an adequate indication following reset.
To avoid sending packets before the Ethernet link is able
to transmit them reliably, you should ensure that the
application does not send packets on the TX client
interface until after the lanes_deskewed signal is asserted.
l<n>_tx_valid
Input When asserted l<n>_tx_data is valid. This signal must be
continuously asserted between the assertions of l<n>_tx_
startofpacket and l<n>_tx_endofpacket for the same
packet.
Figure 3-4: Traffic on the TX and RX Client Interface for 40GbE IP Core Using the Four- to Two-Word
Adapters
Shows typical traffic for the TX and RX Avalon-ST interface 40GbE IP core. This example shows a part of
a ModelSim simulation of the parallel testbench provided with the IP core.
l4_tx_data[255:0]
l4_tx_startofpacket
l4_tx_endofpacket
l4_tx_empty[4:0]
l4_tx_ready
l4_tx_valid
l4_rx_data[255:0]
l4_rx_startofpacket
l4_rx_endofpacket
l4_rx_empty[4:0]
l4_rx_valid
l4_rx_error
2
.
2
.
2
.
2C83
.
2C8300392C8300382C
.
3
.
3
.
3
.
3
.
3
.
3EF9
.
3EF900553EF90054
.
3EF9
.
3EF9
00 0D 00
..
7B44
.
7B44
.
7B44
.
E
.
EFB8
.
EFB8
.
EFB8
.
EFB8
.
EFB8
.
EFB8
.
E
.
EAD
.
EAD2
.
EAD2
.
EAD
.
1E 02 1A
3-8
40-100GbE IP Core TX Data Bus with Adapters (Avalon-ST Interface)
UG-01088
2014.12.15
Altera Corporation
Functional Description
Send Feedback
- MegaCore Function User Guide 1
- Contents 2
- PHY MegaCore Function 4
- 40- or 100-GbE MAC 5
- Device Family Support 7
- IP Core Verification 9
- Simulation Environment 10
- Hardware Testing 10
- Module ALMs Logic Registers 11
- Release Information 21
- Item Description 22
- Getting Started 23
- OpenCore Plus IP Evaluation 24
- IP Core Parameters 25
- Parameter Type Range Default 28
- Parameter Description 28
- Simulating the IP Core 32
- Pin Assignments 33
- 40-100GbE IP Core Testbenches 36
- Testbenches with Adapters 37
- File Names Description 38
- Testbenches without Adapters 40
- Initializing the IP Core 46
- High Level System Overview 49
- 40-100GbE IP Core TX Datapath 50
- Address Insertion 51
- Length/Type Field Processing 52
- Frame Padding 52
- Client Interface 53
- Data Bus Width (Bits) 53
- 40GbE IP Core 100GbE IP Core 53
- 40-100GbE IP Core RX Datapath 67
- RX CRC Forwarding 69
- Address Checking 71
- Inter‑Packet Gap 71
- Pause Ignore 71
- Name Direction Description 73
- 100GbE CAUI–4 PHY 79
- Pause Transmission Logic 82
- Statistics Counters Interface 86
- Name Signal 87
- Direction 87
- Description 87
- Control Data Description 89
- Lane to Lane Deskew Interface 90
- MII Control 91
- MII Data 91
- PCS BER Monitor 92
- Control and Status Interface 98
- Signal Name Description 100
- UG-01088 101
- 2014.12.15 101
- Related Information 102
- Send Feedback 103
- Altera Corporation 103
- Functional Description 103
- Software Interface: Registers 123
- Register Description 124
- 40-100GbE IP Core Registers 126
- Address Name Applicable 128
- Device(s) 128
- Bit Description HW Reset 128
- Bits Description HW Reset 130
- Lock Status Registers 131
- Bit Error Flag Registers 133
- PCS Hardware Error Register 134
- BER Monitor Register 134
- Test Mode Register 135
- Test Pattern Counter Register 135
- MAC and PHY Reset Registers 136
- PCS‑VLANE Registers 138
- PRBS Registers 139
- 40GBASE-KR4 Registers 139
- Pause Registers 149
- MAC Hardware Error Register 151
- CRC Configuration Register 152
- MAC Address Registers 154
- Statistics Registers 155
- PMD Registers 163
- MDIO Registers 164
- Ethernet Glossary 166
- Term Definition 167
- Subscribe 169
- Core v12.0 Release 173
- 10GBASE-KR Registers 174
- Bit R/W Name Description 175
- Additional Information 190
- Date ACDS 191
- at offset 0x127), described 193
- How to Contact Altera 198
- Typographic Conventions 198
- Visual Cue Meaning 199
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