Altera 40-Gbps Ethernet MAC and PHY MegaCore Function Manual de usuario Pagina 3
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40-100GbE IP Core TX Datapath..................................................................................................3-3
40-100GbE IP Core TX Data Bus Interfaces................................................................................3-6
40-100GbE IP Core RX Datapath................................................................................................3-20
40-100GbE IP Core RX Data Bus Interfaces..............................................................................3-25
40GbE Lower Rate 24.24 Gbps MAC and PHY.........................................................................3-32
100GbE CAUI–4 PHY.................................................................................................................. 3-32
External Reconfiguration Controller.......................................................................................... 3-32
Congestion and Flow Control Using Pause Frames................................................................. 3-33
Pause Control and Generation Interface....................................................................................3-35
Pause Control Frame and Non-Pause Control Frame Filtering and Forwarding................3-36
40-100GbE IP Core Modes of Operation ..................................................................................3-37
Link Fault Signaling Interface......................................................................................................3-37
Statistics Counters Interface.........................................................................................................3-39
MAC – PHY XLGMII or CGMII Interface................................................................................3-42
Lane to Lane Deskew Interface.................................................................................................... 3-43
PCS Test Pattern Generation and Test Pattern Check.............................................................3-44
Transceiver PHY Serial Data Interface.......................................................................................3-45
40GBASE-KR4 IP Core Variations............................................................................................. 3-46
Control and Status Interface.........................................................................................................3-51
Clocks.............................................................................................................................................. 3-51
Resets............................................................................................................................................... 3-54
Signals..........................................................................................................................................................3-55
Signals of MAC and PHY Variations Without Adapters.........................................................3-55
Signals of MAC and PHY Variations With Adapters...............................................................3-66
Signals of 40-100GbE MAC-Only IP Core Variations............................................................. 3-68
Signals of 40-100GbE PHY-Only IP Core Variations...............................................................3-72
Software Interface: Registers.................................................................................................................... 3-76
40-100GbE IP Core Registers.......................................................................................................3-79
40-100GbE Example Design Registers......................................................................................3-116
Ethernet Glossary.....................................................................................................................................3-119
Debugging the 40GbE and 100GbE Link............................................................4-1
40-100GbE IP Core Example Design................................................................. A-1
Address Map Changes for the 40-100GbE IP Core v12.0 Release..................... B-1
10GBASE-KR Registers......................................................................................C-1
10GBASE-KR PHY Register Definitions.................................................................................................C-1
Additional Information..................................................................................... D-1
40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide Revision History
..................................................................................................................................................................D-1
How to Contact Altera...............................................................................................................................D-9
Typographic Conventions.........................................................................................................................D-9
40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide
TOC-3
Altera Corporation
- MegaCore Function User Guide 1
- Contents 2
- PHY MegaCore Function 4
- 40- or 100-GbE MAC 5
- Device Family Support 7
- IP Core Verification 9
- Simulation Environment 10
- Hardware Testing 10
- Module ALMs Logic Registers 11
- Release Information 21
- Item Description 22
- Getting Started 23
- OpenCore Plus IP Evaluation 24
- IP Core Parameters 25
- Parameter Type Range Default 28
- Parameter Description 28
- Simulating the IP Core 32
- Pin Assignments 33
- 40-100GbE IP Core Testbenches 36
- Testbenches with Adapters 37
- File Names Description 38
- Testbenches without Adapters 40
- Initializing the IP Core 46
- High Level System Overview 49
- 40-100GbE IP Core TX Datapath 50
- Address Insertion 51
- Length/Type Field Processing 52
- Frame Padding 52
- Client Interface 53
- Data Bus Width (Bits) 53
- 40GbE IP Core 100GbE IP Core 53
- 40-100GbE IP Core RX Datapath 67
- RX CRC Forwarding 69
- Address Checking 71
- Inter‑Packet Gap 71
- Pause Ignore 71
- Name Direction Description 73
- 100GbE CAUI–4 PHY 79
- Pause Transmission Logic 82
- Statistics Counters Interface 86
- Name Signal 87
- Direction 87
- Description 87
- Control Data Description 89
- Lane to Lane Deskew Interface 90
- MII Control 91
- MII Data 91
- PCS BER Monitor 92
- Control and Status Interface 98
- Signal Name Description 100
- UG-01088 101
- 2014.12.15 101
- Related Information 102
- Send Feedback 103
- Altera Corporation 103
- Functional Description 103
- Software Interface: Registers 123
- Register Description 124
- 40-100GbE IP Core Registers 126
- Address Name Applicable 128
- Device(s) 128
- Bit Description HW Reset 128
- Bits Description HW Reset 130
- Lock Status Registers 131
- Bit Error Flag Registers 133
- PCS Hardware Error Register 134
- BER Monitor Register 134
- Test Mode Register 135
- Test Pattern Counter Register 135
- MAC and PHY Reset Registers 136
- PCS‑VLANE Registers 138
- PRBS Registers 139
- 40GBASE-KR4 Registers 139
- Pause Registers 149
- MAC Hardware Error Register 151
- CRC Configuration Register 152
- MAC Address Registers 154
- Statistics Registers 155
- PMD Registers 163
- MDIO Registers 164
- Ethernet Glossary 166
- Term Definition 167
- Subscribe 169
- Core v12.0 Release 173
- 10GBASE-KR Registers 174
- Bit R/W Name Description 175
- Additional Information 190
- Date ACDS 191
- at offset 0x127), described 193
- How to Contact Altera 198
- Typographic Conventions 198
- Visual Cue Meaning 199
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