Altera 40-Gbps Ethernet MAC and PHY MegaCore Function Manual de usuario Pagina 40
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Valorado. / 5. Basado en revisión del cliente
7. At marker 7, the 40GbE IP core asserts l4_rx_valid, indicating that the it has valid data to send to the
client on l4_rx_data[255:0].
8. At marker 8, the 40GbE IP core deasserts l4_rx_valid, indicating that the 40GbE IP core does not
have new valid data to send to the client on l4_rx_data[255:0]. l4_rx_data[255:0] remains
unchanged for a second cycle.
9. At marker 9, the IP core asserts l4_rx_endofpacket, indicating the end of the RX packet.
l4_rx_empty[4:0] has a value of 0x1D, indicating that 29 least significant bytes of the last cycle of the
RX packet empty.
Note: The ready latency on the TX client interface with adapters is 0.
Related Information
Avalon Interface Specifications
For more information about the Avalon-ST protocol.
Testbenches without Adapters
Figure 2-6: 40-100GbE IP Core Testbench Without Adapters
Illustrates the top-level modules of the 40GbE and 100GbE example testbenches that do not use adapters.
In the file names, * denotes 40 for 40GbE IP cores and 100 for 100GbE IP cores.
Transmit MAC
(alt_e*_mac_tx)
CSR MAC
(alt_e*_mac_csr)
Receive MAC
(alt_e*_mac_rx)
Transmit PCS
(alt_e*_pcs_tx)
PHY CSR
(alt_e*_phy_csr)
Receive PCS
(alt_e*_pcs_rx)
PMA
(alt_e*_pma)
MAC (alt_e*_mac) PHY Core (alt_e*_phy)
40GbE and 100GbE MegaCore Function without Adapter (alt_e*)
Packet
Generator
Packet
Checker
Sample
ROM
Test Controller
& Test Result Checker
Memory Map Register
Read/Write Handler
Table 2-7: 40-100GbE IP Core Testbench Without Adapters File Descriptions
Lists the key files that implement the example testbenches.
File Names Description
Testbench and Simulation Files
2-18
Testbenches without Adapters
UG-01088
2014.12.15
Altera Corporation
Getting Started
Send Feedback
- MegaCore Function User Guide 1
- Contents 2
- PHY MegaCore Function 4
- 40- or 100-GbE MAC 5
- Device Family Support 7
- IP Core Verification 9
- Simulation Environment 10
- Hardware Testing 10
- Module ALMs Logic Registers 11
- Release Information 21
- Item Description 22
- Getting Started 23
- OpenCore Plus IP Evaluation 24
- IP Core Parameters 25
- Parameter Type Range Default 28
- Parameter Description 28
- Simulating the IP Core 32
- Pin Assignments 33
- 40-100GbE IP Core Testbenches 36
- Testbenches with Adapters 37
- File Names Description 38
- Testbenches without Adapters 40
- Initializing the IP Core 46
- High Level System Overview 49
- 40-100GbE IP Core TX Datapath 50
- Address Insertion 51
- Length/Type Field Processing 52
- Frame Padding 52
- Client Interface 53
- Data Bus Width (Bits) 53
- 40GbE IP Core 100GbE IP Core 53
- 40-100GbE IP Core RX Datapath 67
- RX CRC Forwarding 69
- Address Checking 71
- Inter‑Packet Gap 71
- Pause Ignore 71
- Name Direction Description 73
- 100GbE CAUI–4 PHY 79
- Pause Transmission Logic 82
- Statistics Counters Interface 86
- Name Signal 87
- Direction 87
- Description 87
- Control Data Description 89
- Lane to Lane Deskew Interface 90
- MII Control 91
- MII Data 91
- PCS BER Monitor 92
- Control and Status Interface 98
- Signal Name Description 100
- UG-01088 101
- 2014.12.15 101
- Related Information 102
- Send Feedback 103
- Altera Corporation 103
- Functional Description 103
- Software Interface: Registers 123
- Register Description 124
- 40-100GbE IP Core Registers 126
- Address Name Applicable 128
- Device(s) 128
- Bit Description HW Reset 128
- Bits Description HW Reset 130
- Lock Status Registers 131
- Bit Error Flag Registers 133
- PCS Hardware Error Register 134
- BER Monitor Register 134
- Test Mode Register 135
- Test Pattern Counter Register 135
- MAC and PHY Reset Registers 136
- PCS‑VLANE Registers 138
- PRBS Registers 139
- 40GBASE-KR4 Registers 139
- Pause Registers 149
- MAC Hardware Error Register 151
- CRC Configuration Register 152
- MAC Address Registers 154
- Statistics Registers 155
- PMD Registers 163
- MDIO Registers 164
- Ethernet Glossary 166
- Term Definition 167
- Subscribe 169
- Core v12.0 Release 173
- 10GBASE-KR Registers 174
- Bit R/W Name Description 175
- Additional Information 190
- Date ACDS 191
- at offset 0x127), described 193
- How to Contact Altera 198
- Typographic Conventions 198
- Visual Cue Meaning 199
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