Altera 40-Gbps Ethernet MAC and PHY MegaCore Function Manual de usuario Pagina 51
- Pagina / 199
- Tabla de contenidos
- MARCADORES
Valorado. / 5. Basado en revisión del cliente
Figure 3-2: Typical Client Frame at the Transmit Interface
Illustrates the changes that the TX MAC makes to the client frame. This figure uses the following
notational conventions:
• <p> = payload size = 0–1500 bytes, or 9600 bytes for jumbo frames.
• <s> = padding bytes = 0–46 bytes.
• <l> = number of IPG bytes
MAC Frame
Added by MAC for TX packets
Destination
Addr[47:0]
SFD[7:0]
Preamble
[47:0]
CRC32
[31:0]
IPG
[<I-1>:0]
PAD [<s>]
Source
Addr[47:0]
Type/
Length[15:0]
Payload
[<p-1>:0]
Start EFD[7:0]
Added by MAC for TX packetsPayload Data from Client
The following sections describe the functions that the TX module performs:
Preamble, Start, and SFD Insertion on page 3-4
Address Insertion on page 3-4
Length/Type Field Processing on page 3-5
Frame Padding on page 3-5
Frame Check Sequence (CRC-32) Insertion on page 3-5
Inter-Packet Gap Generation and Insertion on page 3-5
Preamble, Start, and SFD Insertion
In the TX datapath the MAC appends a one-byte Start, 6-byte preamble, and 1-byte SFD to the client
frame. This MAC module also incorporates the functions of the reconciliation sublayer. The source of the
6-byte preamble and 1-byte SFD depends on whether you turn on the TX preamble pass-through feature
by setting bit 1 of the Preamble Pass-Through Configuration register at offset 0x125.
If the TX preamble pass-through feature is turned on, the client provides the eight-byte preamble (Start
byte, 6-byte preamble, and 1-byte SFD) on the data bus. However, the IP core overwrites the Start byte the
client provides, and only passes on the 6-byte preamble and the SFD. The client is responsible for
providing an appropriate SFD byte.
Related Information
MAC Feature Configuration Registers on page 3-105
Includes information about the Preamble Pass-Through Configuration register.
Address Insertion
The client provides the destination MAC address and the source address of the local MAC. However, if
enabled by bit [31] of the MADDR_CTRL register at offset 0xC2, the source MAC address can be replaced by
the source address contained in two, 32-bit MAC registers: SRC_AD_LO and SRC_AD_HI.
3-4
Preamble, Start, and SFD Insertion
UG-01088
2014.12.15
Altera Corporation
Functional Description
Send Feedback
- MegaCore Function User Guide 1
- Contents 2
- PHY MegaCore Function 4
- 40- or 100-GbE MAC 5
- Device Family Support 7
- IP Core Verification 9
- Simulation Environment 10
- Hardware Testing 10
- Module ALMs Logic Registers 11
- Release Information 21
- Item Description 22
- Getting Started 23
- OpenCore Plus IP Evaluation 24
- IP Core Parameters 25
- Parameter Type Range Default 28
- Parameter Description 28
- Simulating the IP Core 32
- Pin Assignments 33
- 40-100GbE IP Core Testbenches 36
- Testbenches with Adapters 37
- File Names Description 38
- Testbenches without Adapters 40
- Initializing the IP Core 46
- High Level System Overview 49
- 40-100GbE IP Core TX Datapath 50
- Address Insertion 51
- Length/Type Field Processing 52
- Frame Padding 52
- Client Interface 53
- Data Bus Width (Bits) 53
- 40GbE IP Core 100GbE IP Core 53
- 40-100GbE IP Core RX Datapath 67
- RX CRC Forwarding 69
- Address Checking 71
- Inter‑Packet Gap 71
- Pause Ignore 71
- Name Direction Description 73
- 100GbE CAUI–4 PHY 79
- Pause Transmission Logic 82
- Statistics Counters Interface 86
- Name Signal 87
- Direction 87
- Description 87
- Control Data Description 89
- Lane to Lane Deskew Interface 90
- MII Control 91
- MII Data 91
- PCS BER Monitor 92
- Control and Status Interface 98
- Signal Name Description 100
- UG-01088 101
- 2014.12.15 101
- Related Information 102
- Send Feedback 103
- Altera Corporation 103
- Functional Description 103
- Software Interface: Registers 123
- Register Description 124
- 40-100GbE IP Core Registers 126
- Address Name Applicable 128
- Device(s) 128
- Bit Description HW Reset 128
- Bits Description HW Reset 130
- Lock Status Registers 131
- Bit Error Flag Registers 133
- PCS Hardware Error Register 134
- BER Monitor Register 134
- Test Mode Register 135
- Test Pattern Counter Register 135
- MAC and PHY Reset Registers 136
- PCS‑VLANE Registers 138
- PRBS Registers 139
- 40GBASE-KR4 Registers 139
- Pause Registers 149
- MAC Hardware Error Register 151
- CRC Configuration Register 152
- MAC Address Registers 154
- Statistics Registers 155
- PMD Registers 163
- MDIO Registers 164
- Ethernet Glossary 166
- Term Definition 167
- Subscribe 169
- Core v12.0 Release 173
- 10GBASE-KR Registers 174
- Bit R/W Name Description 175
- Additional Information 190
- Date ACDS 191
- at offset 0x127), described 193
- How to Contact Altera 198
- Typographic Conventions 198
- Visual Cue Meaning 199
Relacionado con productos y manuales para Instrumentos de medición Altera 40-Gbps Ethernet MAC and PHY MegaCore Function
(39 paginas)© 2020, manymanuals.es. Todos los derechos reservados | 0.025 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Comentarios a estos manuales