Altera 40-Gbps Ethernet MAC and PHY MegaCore Function Manual de usuario Pagina 173
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Address Map Changes for the 40-100GbE IP
Core v12.0 Release
B
2014.12.15
UG-01088
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Table B-1: Address Map and Register Name Changes for the 40-100GbE IP Core v12.0 Release
For improved organization and clarity, version 12.0 of the 40- and 100-Gbps MAC and PHY MegaCore Function
revised the address map and renamed a few registers. This table lists the address map changes in the 12.0 software
release. These address map changes apply to Stratix IV and Stratix V devices.
Current 40/100GbE
Address
Current Name Previous Address Previous Name
0x017 PCS_HW_ERR HW_ERR
0x018 BER_MONITOR Reserved
0x019 TEST_MODE Reserved
0x01a TEST_PATTERN_
COUNTER
Reserved
0x01b Enable Link Fault
sequence
Reserved
0x01d PHY reset Reserved
0x120 MAC_HW_ERR Reserved
0x121 MAC Reset Reserved
0x122 MAC/RS link fault
sequence configuration
Reserved
0x123 CRC_CONFIG Reserved
0x162-0x17f Reserved 0x160-0x017f DST_ADR
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of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
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101 Innovation Drive, San Jose, CA 95134
- MegaCore Function User Guide 1
- Contents 2
- PHY MegaCore Function 4
- 40- or 100-GbE MAC 5
- Device Family Support 7
- IP Core Verification 9
- Simulation Environment 10
- Hardware Testing 10
- Module ALMs Logic Registers 11
- Release Information 21
- Item Description 22
- Getting Started 23
- OpenCore Plus IP Evaluation 24
- IP Core Parameters 25
- Parameter Type Range Default 28
- Parameter Description 28
- Simulating the IP Core 32
- Pin Assignments 33
- 40-100GbE IP Core Testbenches 36
- Testbenches with Adapters 37
- File Names Description 38
- Testbenches without Adapters 40
- Initializing the IP Core 46
- High Level System Overview 49
- 40-100GbE IP Core TX Datapath 50
- Address Insertion 51
- Length/Type Field Processing 52
- Frame Padding 52
- Client Interface 53
- Data Bus Width (Bits) 53
- 40GbE IP Core 100GbE IP Core 53
- 40-100GbE IP Core RX Datapath 67
- RX CRC Forwarding 69
- Address Checking 71
- Inter‑Packet Gap 71
- Pause Ignore 71
- Name Direction Description 73
- 100GbE CAUI–4 PHY 79
- Pause Transmission Logic 82
- Statistics Counters Interface 86
- Name Signal 87
- Direction 87
- Description 87
- Control Data Description 89
- Lane to Lane Deskew Interface 90
- MII Control 91
- MII Data 91
- PCS BER Monitor 92
- Control and Status Interface 98
- Signal Name Description 100
- UG-01088 101
- 2014.12.15 101
- Related Information 102
- Send Feedback 103
- Altera Corporation 103
- Functional Description 103
- Software Interface: Registers 123
- Register Description 124
- 40-100GbE IP Core Registers 126
- Address Name Applicable 128
- Device(s) 128
- Bit Description HW Reset 128
- Bits Description HW Reset 130
- Lock Status Registers 131
- Bit Error Flag Registers 133
- PCS Hardware Error Register 134
- BER Monitor Register 134
- Test Mode Register 135
- Test Pattern Counter Register 135
- MAC and PHY Reset Registers 136
- PCS‑VLANE Registers 138
- PRBS Registers 139
- 40GBASE-KR4 Registers 139
- Pause Registers 149
- MAC Hardware Error Register 151
- CRC Configuration Register 152
- MAC Address Registers 154
- Statistics Registers 155
- PMD Registers 163
- MDIO Registers 164
- Ethernet Glossary 166
- Term Definition 167
- Subscribe 169
- Core v12.0 Release 173
- 10GBASE-KR Registers 174
- Bit R/W Name Description 175
- Additional Information 190
- Date ACDS 191
- at offset 0x127), described 193
- How to Contact Altera 198
- Typographic Conventions 198
- Visual Cue Meaning 199
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