Altera 40-Gbps Ethernet MAC and PHY MegaCore Function Manual de usuario Pagina 125
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Word Offset Register Description
0x118–0x11F Reserved.
0x120 MAC hardware error register.
0x121 MAC reset register.
0x122 One of two link fault signaling registers.
0x123 CRC configuration register.
0x124 Padding configuration register. One of the MAC feature configuration
registers.
0x125 Preamble pass-through configuration register. One of the MAC feature
configuration registers.
0x126–0x127 IPG adjustment registers. Two of the MAC feature configuration registers.
0x140–0x17F MAC address registers.
0x180–0x1FF Reserved.
0x200–0x229 Transmit side statistics registers that are not TX packet statistics registers.
0x22A–0x22D TX Packet Statistics.
0x22E–0x27F Reserved.
0x280–0x2A9 Receive side statistics registers that are not RX packet statistics registers.
0x2AA–0x2B8 RX packet statistics registers.
0x2B9–0x3FF Reserved.
0x400–0x423 40-100GbE example design registers. Refer to the following table.
0x800-0x9FF
Altera’s Low Latency PHY IP core registers, for use with the CAUI-4
configuration only. Offsets 0x800-0x9FF are for CAUI-4 lane 1, offsets
0xA00-0xBFF are for CAUI-4 lane 2, offsets 0xC00-0xDFF are for CAUI-4
lane 3, and offsets 0xE00-0xFFF are for CAUI-4 lane 4. Each lane maps to
word addresses 0x000-0x1FF for one low latency PHY transceiver channel.
0xA00-0xBFF
0xC00-0xDFF
0xE00-0xFFF
3-78
Software Interface: Registers
UG-01088
2014.12.15
Altera Corporation
Functional Description
Send Feedback
- MegaCore Function User Guide 1
- Contents 2
- PHY MegaCore Function 4
- 40- or 100-GbE MAC 5
- Device Family Support 7
- IP Core Verification 9
- Simulation Environment 10
- Hardware Testing 10
- Module ALMs Logic Registers 11
- Release Information 21
- Item Description 22
- Getting Started 23
- OpenCore Plus IP Evaluation 24
- IP Core Parameters 25
- Parameter Type Range Default 28
- Parameter Description 28
- Simulating the IP Core 32
- Pin Assignments 33
- 40-100GbE IP Core Testbenches 36
- Testbenches with Adapters 37
- File Names Description 38
- Testbenches without Adapters 40
- Initializing the IP Core 46
- High Level System Overview 49
- 40-100GbE IP Core TX Datapath 50
- Address Insertion 51
- Length/Type Field Processing 52
- Frame Padding 52
- Client Interface 53
- Data Bus Width (Bits) 53
- 40GbE IP Core 100GbE IP Core 53
- 40-100GbE IP Core RX Datapath 67
- RX CRC Forwarding 69
- Address Checking 71
- Inter‑Packet Gap 71
- Pause Ignore 71
- Name Direction Description 73
- 100GbE CAUI–4 PHY 79
- Pause Transmission Logic 82
- Statistics Counters Interface 86
- Name Signal 87
- Direction 87
- Description 87
- Control Data Description 89
- Lane to Lane Deskew Interface 90
- MII Control 91
- MII Data 91
- PCS BER Monitor 92
- Control and Status Interface 98
- Signal Name Description 100
- UG-01088 101
- 2014.12.15 101
- Related Information 102
- Send Feedback 103
- Altera Corporation 103
- Functional Description 103
- Software Interface: Registers 123
- Register Description 124
- 40-100GbE IP Core Registers 126
- Address Name Applicable 128
- Device(s) 128
- Bit Description HW Reset 128
- Bits Description HW Reset 130
- Lock Status Registers 131
- Bit Error Flag Registers 133
- PCS Hardware Error Register 134
- BER Monitor Register 134
- Test Mode Register 135
- Test Pattern Counter Register 135
- MAC and PHY Reset Registers 136
- PCS‑VLANE Registers 138
- PRBS Registers 139
- 40GBASE-KR4 Registers 139
- Pause Registers 149
- MAC Hardware Error Register 151
- CRC Configuration Register 152
- MAC Address Registers 154
- Statistics Registers 155
- PMD Registers 163
- MDIO Registers 164
- Ethernet Glossary 166
- Term Definition 167
- Subscribe 169
- Core v12.0 Release 173
- 10GBASE-KR Registers 174
- Bit R/W Name Description 175
- Additional Information 190
- Date ACDS 191
- at offset 0x127), described 193
- How to Contact Altera 198
- Typographic Conventions 198
- Visual Cue Meaning 199
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