Altera Stratix V Avalon-ST Manual de usuario Pagina 173

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Figure 10-2: Architecture of the Transaction Layer: Dedicated Receive Buffer
Transaction Layer TX Datapath
Transaction Layer RX Datapath
Avalon-ST
RX Control
Configuration Space
TLPs to
Data Link Layer
RX Transaction
Layer Packet
Avalon-ST RX Data
Avalon-ST
TX Data
to Application Layer
ConfigurationRequests
Reordering
RX Buffer
Posted & Completion
Non-Posted
Flow Control Update
Transaction Layer
Packet FIFO
Width
Adapter
( <256
bits)
Packet
Alignment
TX
Control
RX
Control
TX Flow
Control
Configuration Space
The Configuration Space implements the following configuration registers and associated functions:
Header Type 0 Configuration Space for Endpoints
Header Type 1 Configuration Space for Root Ports
PCI Power Management Capability Structure
Virtual Channel Capability Structure
Message Signaled Interrupt (MSI) Capability Structure
Message Signaled Interrupt–X (MSI–X) Capability Structure
PCI Express Capability Structure
Advanced Error Reporting (AER) Capability Structure
Vendor Specific Extended Capability (VSEC)
10-6
Configuration Space
UG-01097_avst
2014.08.18
Altera Corporation
IP Core Architecture
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