Altera MAX 10 Embedded Memory Manual de usuario descargar pdf (Pagina 42)

Option Legal Values Description

Create one clock enable signal for each

clock signal.

On/Off Specifies whether to turn on

the option to create one

clock enable signal for each

clock signal.

More Option When you select With

one read port and one

write port, the

following option is

available:

• Clock enable

options

• Clock enable

options: Use

clock enable for

write input

registers

• Address options

• Create an ‘wr_

addressstall’

input port.

• Create an ‘rd_

addressstall’

input port.

When you select With

two read /write ports,

the following options

are available:

• Clock enable

options

• Use clock enable

for port A input

registers

• Use clock enable

for port A

output registers

• Address options

• Create an

‘addressstall_a’

input port.

• Create an

‘addressstall_b’

input port.

On/Off

• Clock enable options—

Clock enable for port B

input and output

registers are turned on by

default. You only need to

specify whether to use

clock enable for port A

input and output

registers.

• Address options—

Specifies whether to

create clock enables for

address registers. You can

create these ports to act

as an extra active low

clock enable input for the

address registers.

Create an ‘aclr’ asynchronous clear for the

registered ports.

On/Off Specifies whether to create

an asynchronous clear port

for the registered ports.

5-14

RAM: 2-Port IP Core Parameters for MAX 10 Devices

UG-M10MEMORY

2015.05.04

Altera Corporation

RAM: 2-PORT IP Core References

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