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Port Name Required Description
reset_n No Asynchronous active low reset port.
a_data Yes Matrix A input data.
a_valid Yes Matrix A Avalon streaming valid signal. When this signal is
asserted, data on a_data is valid.
b_data Yes Matrix B input data.
b_valid Yes Matrix B Avalon streaming valid signal. When this signal is asserted,
data on b_data is valid.
c_ready Yes Matrix C Avalon streaming ready signal. Ready latency is 0.
Table 3-3: ALTERA_FP_MATRIX_MULT Output Signals
Port Name Required Description
a_ready Yes Matrix A Avalon streaming ready signal. Ready latency is 0.
b_ready Yes Matrix B Avalon streaming ready signal. Ready latency is 0.
c_data Yes Matrix C input data.
c_valid Yes Matrix C Avalon streaming valid signal. When this signal is asserted,
data on c_data is valid.
ALTERA_FP_MATRIX_MULT Parameters
This table lists the parameters for the ALTERA_FP_MATRIX_MULT IP core.
Table 3-4: ALTERA_FP_MATRIX_MULT IP Core Parameters
Parameter Value Description
Format Single (32 bit) or Double
(64 bit)
The format of the input data.
Rows in Matrix A 2-256 Number of rows in matrix A.
Columns in Matrix A 8-256 Integer multiples of
vector size. (Integer
multiples of Memory
Blocks.)
Number of columns in matrix A. This
is also the number of rows in matrix
B.
Rows in Matrix B 8-256 Number of rows in matrix B.
Columns of matrix B 2-256 Number of columns in matrix B.
UG-01058
2014.12.19
ALTERA_FP_MATRIX_MULT Parameters
3-5
ALTERA_FP_MATRIX_MULT IP Core
Altera Corporation
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- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About Floating-Point IP Cores 7
- Design Flow 8
- Using the Parameter Editor 10
- File Name Description 12
- Upgrading IP Cores 15
- Related Information 18
- Floating-Point Formats 19
- Special Case Numbers 20
- Non-IEEE-754 Standard Format 21
- Integer bits 22
- Fraction bits 22
- VHDL Component Declaration 24
- VHDL LIBRARY-USE Declaration 24
- ALTERA_FP_MATRIX_INV IP Core 25
- Triangular Matrix Inversion 29
- Matrix Multiplication 29
- Matrix Inversion Operation 29
- Precision Format Numbers 30
- Sample Matrix Data 32
- Matrix Data 33
- ALTERA_FP_MATRIX_INV Signals 34
- ALTERA_FP_MATRIX_MULT IP Core 36
- . . . N-10 . . 38
- . . . N-10 38
- ALTERA_FP_MATRIX_MULT 39
- Parameter Value Description 40
- ALTERA_FP_ACC_CUSTOM IP Core 42
- ALTERA_FP_ACC_CUSTOM Signals 44
- ALTFP_ADD_SUB IP Core 48
- ALTFP_ADD_SUB Signals 51
- ALTFP_ADD_SUB 52
- ALTFP_ADD_SUB Parameters 53
- ALTFP_DIV IP Core 55
- ALTFP_DIV Truth Table 56
- ALTFP_DIV Signals 60
- ALTFP_DIV Parameters 61
- ALTFP_MULT IP Core 63
- Parameters 66
- ALTFP_MULT Signals 67
- ALTFP_SQRT 69
- ALTFP_SQRT Truth Table 70
- ALTFP_SQRT Signals 72
- ALTFP_SQRT Parameters 74
- ALTFP_EXP IP Core 75
- ALTFP_EXP Signals 78
- ALTFP_EXP 79
- ALTFP_EXP Parameters 80
- ALTFP_INV IP Core 81
- ALTFP_INV_SQRT IP Core 87
- ALTFP_INV_SQRT 90
- ALTFP_LOG 93
- ALTFP_ATAN IP Core 99
- ALTFP_ATAN Parameters 100
- Parameter 101
- Type Required Description 101
- ALTFP_SINCOS IP Core 102
- ALTFP_SINCOS Signals 103
- ALTFP_SINCOS Parameters 104
- ALTFP_ABS IP Core 105
- UG-01058 106
- 2014.12.19 106
- ALTFP_ABS Signals 107
- ALTFP_ABS 108
- ALTFP_ABS Parameters 109
- ALTFP_COMPARE IP Core 111
- Format Numbers 112
- ALTFP_COMPARE Signals 113
- ALTFP_COMPARE Parameters 114
- ALTFP_CONVERT IP Core 116
- ALTFP_CONVERT Output Latency 117
- Point Format Numbers 121
- Time Event 122
- ALTFP_CONVERT Signals 123
- ALTFP_CONVERT Parameters 125
- ALTERA_FP_FUNCTIONS IP Core 128
- Function Description 129
- ALTERA_FP_FUNCTIONS Signals 151
- Altera Corporation 152
- Send Feedback 152
- Document Revision History 156
- Date Document 157
- Changes Made 157
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