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Port Name Required Description
done Yes When asserted, the last output has been written. A new matrix
multiply can be started with calculate. done will follow ready by
some fixed amount, depending on the parameters.
ALTERA_FP_MATRIX_INV Parameters
Table 2-6: ALTERA_FP_MATRIX_INV Parameters
Port Name Type Required Description
BLOCKS Integer No The number of memory blocks for the double-buffered
storage of matrix multiplication. The allowable range is
from 2 to 16.
DIMENSION Integer Yes The number of rows in the matrix. As the matrix is
square, this is also the number of columns in the matrix.
The supported dimensions are 4 x 4, 6 x 6, 8 x 8, 16 x 16,
32 x 32, and 64 x 64. The maximum supported input
dimension is 64 × 64.
This parameter also acts as the VECTORSIZE when
calling the ALTERA_FP_MATRIX_MULT IP core
internally.
WIDTH_EXP Integer Yes Specifies the precision of the exponent. The bias of the
exponent is always set to 2(WIDTH_EXP-1) -1 (that is,
127 for single-precision format). WIDTH_EXP must be 8 for
single-precision format and must be less than WIDTH_MAN.
The available value for WIDTH_EXP is 8.
WIDTH_MAN Integer Yes Specifies the precision of the mantissa. WIDTH_MAN must
be 23 when WIDTH_EXP is 8. Otherwise, WIDTH_MAN must
be a minimum of 31. WIDTH_MAN must be greater than
WIDTH_EXP. The sum of WIDTH_EXP and WIDTH_MAN must
be less than 64. Current available value for WIDTH_MAN is
only 23 for single precision.
UG-01058
2014.12.19
ALTERA_FP_MATRIX_INV Parameters
2-11
ALTERA_FP_MATRIX_INV IP Core
Altera Corporation
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- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About Floating-Point IP Cores 7
- Design Flow 8
- Using the Parameter Editor 10
- File Name Description 12
- Upgrading IP Cores 15
- Related Information 18
- Floating-Point Formats 19
- Special Case Numbers 20
- Non-IEEE-754 Standard Format 21
- Integer bits 22
- Fraction bits 22
- VHDL Component Declaration 24
- VHDL LIBRARY-USE Declaration 24
- ALTERA_FP_MATRIX_INV IP Core 25
- Triangular Matrix Inversion 29
- Matrix Multiplication 29
- Matrix Inversion Operation 29
- Precision Format Numbers 30
- Sample Matrix Data 32
- Matrix Data 33
- ALTERA_FP_MATRIX_INV Signals 34
- ALTERA_FP_MATRIX_MULT IP Core 36
- . . . N-10 . . 38
- . . . N-10 38
- ALTERA_FP_MATRIX_MULT 39
- Parameter Value Description 40
- ALTERA_FP_ACC_CUSTOM IP Core 42
- ALTERA_FP_ACC_CUSTOM Signals 44
- ALTFP_ADD_SUB IP Core 48
- ALTFP_ADD_SUB Signals 51
- ALTFP_ADD_SUB 52
- ALTFP_ADD_SUB Parameters 53
- ALTFP_DIV IP Core 55
- ALTFP_DIV Truth Table 56
- ALTFP_DIV Signals 60
- ALTFP_DIV Parameters 61
- ALTFP_MULT IP Core 63
- Parameters 66
- ALTFP_MULT Signals 67
- ALTFP_SQRT 69
- ALTFP_SQRT Truth Table 70
- ALTFP_SQRT Signals 72
- ALTFP_SQRT Parameters 74
- ALTFP_EXP IP Core 75
- ALTFP_EXP Signals 78
- ALTFP_EXP 79
- ALTFP_EXP Parameters 80
- ALTFP_INV IP Core 81
- ALTFP_INV_SQRT IP Core 87
- ALTFP_INV_SQRT 90
- ALTFP_LOG 93
- ALTFP_ATAN IP Core 99
- ALTFP_ATAN Parameters 100
- Parameter 101
- Type Required Description 101
- ALTFP_SINCOS IP Core 102
- ALTFP_SINCOS Signals 103
- ALTFP_SINCOS Parameters 104
- ALTFP_ABS IP Core 105
- UG-01058 106
- 2014.12.19 106
- ALTFP_ABS Signals 107
- ALTFP_ABS 108
- ALTFP_ABS Parameters 109
- ALTFP_COMPARE IP Core 111
- Format Numbers 112
- ALTFP_COMPARE Signals 113
- ALTFP_COMPARE Parameters 114
- ALTFP_CONVERT IP Core 116
- ALTFP_CONVERT Output Latency 117
- Point Format Numbers 121
- Time Event 122
- ALTFP_CONVERT Signals 123
- ALTFP_CONVERT Parameters 125
- ALTERA_FP_FUNCTIONS IP Core 128
- Function Description 129
- ALTERA_FP_FUNCTIONS Signals 151
- Altera Corporation 152
- Send Feedback 152
- Document Revision History 156
- Date Document 157
- Changes Made 157
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