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Additional Information
B
2015.05.04
UG-01140
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Document Revision History
Table B-1: 50G Interlaken MegaCore Function User Guide Revision History
Date ACDS Version Changes Made
2015.05
.04
15.0
• Added new TX scrambler seed parameter in new section TX Scrambler Seed
on page 3-2. Previously this parameter was hidden (SCRAM_CONST) and
unavailable for Arria 10 devices. In the IP core version 15.0 and later, you
must modify the scrambler seed from the parameter editor.
• Improved description of itx_ifc_err output signal in 50G Interlaken IP Core
User Data Transfer Interface Signals on page 5-4.
• Improved description of itx_hungry output signal in 50G Interlaken IP Core
Interlaken Link and Miscellaneous Interface Signals on page 5-8.
• Updated filenames for hidden parameter editing to include the filenames for
Arria 10 variations, in Modifying Hidden Parameter Values on page 9-4.
2014.12
.15
14.1
• Updated release-specific information for the software release v14.1, including
new resource utilization numbers and new Arria 10 speed grade notation and
information. Resource utilization numbers improved by 20% in the v14.0
release.
• Updated for new Quartus II IP Catalog, which replaces the MegaWizard Plug-
In Manager starting in the Quartus II software v14.0. Changes are located
primarily in Getting Started with the 50G Interlaken IP Core chapter.
Reordered the chapter to accommodate the new descriptions.
• Corrected instructions to connect the external TX PLL to include the tx_cal_
busy signal, and added example figure to illustrate the required connections
between the IP core and an ATX PLL. Changes are located in Adding the
External PLL section. .
• Added information about the required wait from reset to successful register
access in IP Core Reset section. .
• Corrected width of reconfig_waitrequest signal to one bit. This signal has
been a single bit in all versions that support Arria 10 devices, starting with the
IP core version 13.1 Arria 10 Edition.
©
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
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9001:2008
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101 Innovation Drive, San Jose, CA 95134
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About This MegaCore Function 3
- Device Family Support 6
- IP Core Verification 7
- Device Speed Grade Support 8
- Release Information 8
- Altera IP Core Release Notes 9
- OpenCore Plus IP Evaluation 10
- UG-01140 11
- 2015.05.04 11
- Related Information 12
- 10 variation 13
- Pin Assignments 15
- Send Feedback 16
- Altera Corporation 16
- Adding the External PLL 21
- 50G Interlaken IP Core 22
- Meta Frame Length in Words 24
- Number of Calendar Pages 25
- TX Scrambler Seed 25
- Transfer Mode Selection 25
- Functional Description 27
- Management Interface 28
- High Level Block Diagram 30
- IP Core Reset 31
- Interleaved and Packet Modes 33
- 50G Interlaken IP Core TX MAC 40
- 50G Interlaken IP Core TX PCS 40
- 50G Interlaken IP Core TX PMA 40
- 50G Interlaken IP Core RX PMA 45
- 50G Interlaken IP Core RX PCS 45
- 50G Interlaken IP Core RX MAC 45
- Signal Name Direction Width 47
- Description 47
- Device Dependent Signals 60
- Offset Name R/W Description 63
- Example Design 68
- Top Testbench 68
- Testbench Simulation Behavior 70
- Internal Serial Loopback Mode 72
- External Loopback Mode 72
- CRC32 Error Injection 78
- Advanced Parameter Settings 79
- Counter Reset Bits 80
- Include Temp Sense 80
- RXFIFO Address Width 80
- Use ATX or CMU PLL 82
- Lane Profile 82
- MegaCore Function 84
- Ethernet Traffic 89
- Additional Information 91
- How to Contact Altera 93
- Typographic Conventions 93
- Visual Cue Meaning 94
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