Altera 50G Interlaken MegaCore Function Manual de usuario Pagina 34
- Pagina / 94
- Tabla de contenidos
- MARCADORES
Valorado. / 5. Basado en revisión del cliente
In Packet mode, the 50G Interlaken IP Core performs Optional Scheduling Enhancement based on
Section 5.3.2.1.1 of the Interlaken Protocol Specification, Revision 1.2. The IP core ignores the itx_sob and
itx_eob signals. Instead, the IP core performs optional enhanced scheduling based on the settings of
BurstMax, BurstMin, and BurstShort.
In Interleaved mode, the 50G Interlaken IP Core inserts burst control words on the Interlaken link based
on the itx_sob and itx_eob inputs. The internal optional enhanced scheduling is disabled and the
BurstMax and BurstMin values are ignored. BurstShort is still in effect. To avoid overflowing the transmit
FIFO, you should not send a burst that is longer than 1024 bytes.
In Interleaved mode or in Packet mode, the 50G Interlaken IP core is capable of accepting non-
interleaved data on the TX user data transfer interface (itx_din_words). However, if the IP core is in
Interleaved mode, the application must drive the itx_sob and itx_eob inputs correctly.
In Interleaved mode or in Packet mode, the 50G Interlaken IP core can generate interleaved data transfers
on the RX user data transfer interface (irx_dout_words). The application must be able to accept
interleaved data transfers if the Interlaken link partner transmits them on the Interlaken link. In this case,
the Interlaken link partner must send traffic in Interleaved mode that conforms with the 50G Interlaken
IP core BurstShort value.
Note: Altera recommends that the transmitter (link partner) only send packets with a minimum packet
size of 64 bytes.
Related Information
• Transfer Mode Selection on page 3-2
• 50G Interlaken IP Core User Data Transfer Interface Signals on page 5-4
• Interlaken Protocol Specification, Revision 1.2
50G Interlaken IP Core Transmit Path
The 50G Interlaken MegaCore function accepts application data from up to 256 channels and combines it
into a single data stream in which data is labeled with its source channel. The 50G Interlaken TX MAC
and PCS blocks format the data into protocol-compliant bursts and insert Idle words where required.
50G Interlaken IP Core Transmit User Data Interface Examples
The following examples illustrate how to use the Altera 50G Interlaken IP core TX user data interface:
50G Interlaken IP Core Interleaved Mode (Segmented Mode) Example on page 4-8
50G Interlaken IP Core Packet Mode Operation Example on page 4-10
50G Interlaken IP Core Back-Pressured Packet Transfer Example on page 4-11
50G Interlaken IP Core Interleaved Mode (Segmented Mode) Example
In Interleaved Mode, you are responsible for scheduling the burst. You need to drive an extra pair of
signals, Start of Burst (SOB) and End of Burst (EOB), to indicate the burst boundary. You can send the
traffic in packet order or interleaved order, as long as you set the SOB and EOB flags correctly to establish
the data boundaries.
4-8
50G Interlaken IP Core Transmit Path
UG-01140
2015.05.04
Altera Corporation
Functional Description
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About This MegaCore Function 3
- Device Family Support 6
- IP Core Verification 7
- Device Speed Grade Support 8
- Release Information 8
- Altera IP Core Release Notes 9
- OpenCore Plus IP Evaluation 10
- UG-01140 11
- 2015.05.04 11
- Related Information 12
- 10 variation 13
- Pin Assignments 15
- Send Feedback 16
- Altera Corporation 16
- Adding the External PLL 21
- 50G Interlaken IP Core 22
- Meta Frame Length in Words 24
- Number of Calendar Pages 25
- TX Scrambler Seed 25
- Transfer Mode Selection 25
- Functional Description 27
- Management Interface 28
- High Level Block Diagram 30
- IP Core Reset 31
- Interleaved and Packet Modes 33
- 50G Interlaken IP Core TX MAC 40
- 50G Interlaken IP Core TX PCS 40
- 50G Interlaken IP Core TX PMA 40
- 50G Interlaken IP Core RX PMA 45
- 50G Interlaken IP Core RX PCS 45
- 50G Interlaken IP Core RX MAC 45
- Signal Name Direction Width 47
- Description 47
- Device Dependent Signals 60
- Offset Name R/W Description 63
- Example Design 68
- Top Testbench 68
- Testbench Simulation Behavior 70
- Internal Serial Loopback Mode 72
- External Loopback Mode 72
- CRC32 Error Injection 78
- Advanced Parameter Settings 79
- Counter Reset Bits 80
- Include Temp Sense 80
- RXFIFO Address Width 80
- Use ATX or CMU PLL 82
- Lane Profile 82
- MegaCore Function 84
- Ethernet Traffic 89
- Additional Information 91
- How to Contact Altera 93
- Typographic Conventions 93
- Visual Cue Meaning 94
Relacionado con productos y manuales para Instrumentos de medición Altera 50G Interlaken MegaCore Function
Instrumentos de medición Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core Manual de usuario
(11 paginas)
(11 paginas)
Instrumentos de medición Altera Embedded Systems Development Kit, Cyclone III Edit Manual de usuario
(82 paginas)
(82 paginas)
© 2020, manymanuals.es. Todos los derechos reservados | 0.032 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Comentarios a estos manuales