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Signal Name Direction Width
(Bits)
Description
irx_sop Output 1 Indicates the current data symbol on irx_dout_words contains the
start of a packet (SOP). This signal has the following valid values:
• 1'b0—The current data symbol does not contain the start of a
packet.
• 1'b1—The current data symbol contains the start of a packet.
irx_
eopbits
Output 4 Indicates whether the current data symbol contains the end of a packet
(EOP) with or without an error, and specifies the number of valid bytes
in the current end-of-packet, non-error 8-byte data word, if relevant.
The IP core sets the value of irx_eopbits as follows:
• 4b’0000: no end of packet, no error.
• 4b’0001: Error and end of packet.
• 4b’1xxx: End of packet. xxx indicates the number of valid bytes in
the final valid 8-byte word of the packet, as follows:
• 3b’000: all 8 bytes are valid.
• 3b’001: 1 byte is valid.
• ...
• 3b’111: 7 bytes are valid.
All other values (4'b01xx, 4'b001x) are undefined and are not generated
by the IP core.
The valid bytes always start in bit positions [63:56] of the final valid
data word of the packet.
irx_sob Output 1 Start of the burst. The 50G Interlaken IP core indicates the start of the
burst. The signal irx_channel is only valid when irx_sob is high. This
signal toggles in Packet Mode and in Interleaved Mode.
This signal has the following valid values:
• 1'b0—The current data symbol does not contain the start of a burst.
• 1'b1—The current data symbol contains the start of a burst.
irx_eob Output 1 End of the burst. The 50G Interlaken IP core indicates the end of the
burst. This signal toggles in Packet Mode and in Interleaved Mode.
irx_dout_
words
Output
256
The four 64-bit words of output data (one data symbol). When irx_
num_valid has the value of zero, you should ignore irx_dout_words.
irx_
calendar
Output 16 × N Multiple pages (16 bits per page) of calendar output bits. The value is
the in-band flow control bits from N control words on the incoming
Interlaken link. N is the value of the Number of calendar pages
parameter, which can be any of 1, 2, 4, 8, or 16. This signal is synchro‐
nous with rx_usr_clk, although it is not part of the user data transfer
protocol.
UG-01140
2015.05.04
50G Interlaken IP Core User Data Transfer Interface Signals
5-7
50G Interlaken MegaCore Function Signals
Altera Corporation
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- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About This MegaCore Function 3
- Device Family Support 6
- IP Core Verification 7
- Device Speed Grade Support 8
- Release Information 8
- Altera IP Core Release Notes 9
- OpenCore Plus IP Evaluation 10
- UG-01140 11
- 2015.05.04 11
- Related Information 12
- 10 variation 13
- Pin Assignments 15
- Send Feedback 16
- Altera Corporation 16
- Adding the External PLL 21
- 50G Interlaken IP Core 22
- Meta Frame Length in Words 24
- Number of Calendar Pages 25
- TX Scrambler Seed 25
- Transfer Mode Selection 25
- Functional Description 27
- Management Interface 28
- High Level Block Diagram 30
- IP Core Reset 31
- Interleaved and Packet Modes 33
- 50G Interlaken IP Core TX MAC 40
- 50G Interlaken IP Core TX PCS 40
- 50G Interlaken IP Core TX PMA 40
- 50G Interlaken IP Core RX PMA 45
- 50G Interlaken IP Core RX PCS 45
- 50G Interlaken IP Core RX MAC 45
- Signal Name Direction Width 47
- Description 47
- Device Dependent Signals 60
- Offset Name R/W Description 63
- Example Design 68
- Top Testbench 68
- Testbench Simulation Behavior 70
- Internal Serial Loopback Mode 72
- External Loopback Mode 72
- CRC32 Error Injection 78
- Advanced Parameter Settings 79
- Counter Reset Bits 80
- Include Temp Sense 80
- RXFIFO Address Width 80
- Use ATX or CMU PLL 82
- Lane Profile 82
- MegaCore Function 84
- Ethernet Traffic 89
- Additional Information 91
- How to Contact Altera 93
- Typographic Conventions 93
- Visual Cue Meaning 94
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