Altera 50G Interlaken MegaCore Function Manual de usuario Pagina 4
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Counter Reset Bits............................................................................................................................9-2
Include Temp Sense.........................................................................................................................9-2
RXFIFO Address Width..................................................................................................................9-2
SWAP_TX_LANES and SWAP_RX_LANES (Data Word Lane Swapping)..........................9-2
Use ATX or CMU PLL....................................................................................................................9-4
Lane Profile.......................................................................................................................................9-4
Modifying Hidden Parameter Values.......................................................................................................9-4
Out-of-Band Flow Control in the 50G Interlaken MegaCore Function..........10-1
Out-of-Band Flow Control Block Clocks...............................................................................................10-2
TX Out-of-Band Flow Control Signals...................................................................................................10-2
RX Out-of-Band Flow Control Signals...................................................................................................10-4
Performance and Fmax Requirements for 40G Ethernet Traffic..................... A-1
Additional Information......................................................................................B-1
Document Revision History...................................................................................................................... B-1
How to Contact Altera................................................................................................................................B-3
Typographic Conventions..........................................................................................................................B-3
TOC-4
About This MegaCore Function
Altera Corporation
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About This MegaCore Function 3
- Device Family Support 6
- IP Core Verification 7
- Device Speed Grade Support 8
- Release Information 8
- Altera IP Core Release Notes 9
- OpenCore Plus IP Evaluation 10
- UG-01140 11
- 2015.05.04 11
- Related Information 12
- 10 variation 13
- Pin Assignments 15
- Send Feedback 16
- Altera Corporation 16
- Adding the External PLL 21
- 50G Interlaken IP Core 22
- Meta Frame Length in Words 24
- Number of Calendar Pages 25
- TX Scrambler Seed 25
- Transfer Mode Selection 25
- Functional Description 27
- Management Interface 28
- High Level Block Diagram 30
- IP Core Reset 31
- Interleaved and Packet Modes 33
- 50G Interlaken IP Core TX MAC 40
- 50G Interlaken IP Core TX PCS 40
- 50G Interlaken IP Core TX PMA 40
- 50G Interlaken IP Core RX PMA 45
- 50G Interlaken IP Core RX PCS 45
- 50G Interlaken IP Core RX MAC 45
- Signal Name Direction Width 47
- Description 47
- Device Dependent Signals 60
- Offset Name R/W Description 63
- Example Design 68
- Top Testbench 68
- Testbench Simulation Behavior 70
- Internal Serial Loopback Mode 72
- External Loopback Mode 72
- CRC32 Error Injection 78
- Advanced Parameter Settings 79
- Counter Reset Bits 80
- Include Temp Sense 80
- RXFIFO Address Width 80
- Use ATX or CMU PLL 82
- Lane Profile 82
- MegaCore Function 84
- Ethernet Traffic 89
- Additional Information 91
- How to Contact Altera 93
- Typographic Conventions 93
- Visual Cue Meaning 94
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