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Advanced Parameter Settings
9
2015.05.04
UG-01140
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Advanced users can further customize the 50G Interlaken IP core by modifying hidden parameters that
are not displayed in the 50G Interlaken parameter editor. These parameters can only be modified in the
Verilog RTL instantiation in the generated ilk_core_50g.sv file and the instantiation of the 50G Interlaken
IP core in the top level design file.
The following topics describe the hidden parameters and tell you how to modify their values.
Hidden Parameters on page 9-1
Modifying Hidden Parameter Values on page 9-4
Hidden Parameters
The advanced parameters affect the behavior of the 50G Interlaken MegaCore function.
Note:
Altera recommends that you do not modify any RTL parameters that are not listed here. Some
undocumented modifications might overwrite settings you specify in the parameter editor.
To customize your 50G Interlaken MegaCore function, you can modify parameters to specify the
following properties:
Required User Clock Frequency on page 9-1
Counter Reset Bits on page 9-2
Include Temp Sense on page 9-2
RXFIFO Address Width on page 9-2
SWAP_TX_LANES and SWAP_RX_LANES (Data Word Lane Swapping) on page 9-2
Use ATX or CMU PLL on page 9-4
Lane Profile on page 9-4
Required User Clock Frequency
The TX_USR_CLK_MHZ parameter specifies the expected frequency of the input clocks tx_usr_clk and
rx_usr_clk.
The default value of this parameter is 250 MHz. The range of allowed values is 200 MHz to 300 MHz. You
must drive the two input clocks at the frequency specified by this parameter.
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of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
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101 Innovation Drive, San Jose, CA 95134
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About This MegaCore Function 3
- Device Family Support 6
- IP Core Verification 7
- Device Speed Grade Support 8
- Release Information 8
- Altera IP Core Release Notes 9
- OpenCore Plus IP Evaluation 10
- UG-01140 11
- 2015.05.04 11
- Related Information 12
- 10 variation 13
- Pin Assignments 15
- Send Feedback 16
- Altera Corporation 16
- Adding the External PLL 21
- 50G Interlaken IP Core 22
- Meta Frame Length in Words 24
- Number of Calendar Pages 25
- TX Scrambler Seed 25
- Transfer Mode Selection 25
- Functional Description 27
- Management Interface 28
- High Level Block Diagram 30
- IP Core Reset 31
- Interleaved and Packet Modes 33
- 50G Interlaken IP Core TX MAC 40
- 50G Interlaken IP Core TX PCS 40
- 50G Interlaken IP Core TX PMA 40
- 50G Interlaken IP Core RX PMA 45
- 50G Interlaken IP Core RX PCS 45
- 50G Interlaken IP Core RX MAC 45
- Signal Name Direction Width 47
- Description 47
- Device Dependent Signals 60
- Offset Name R/W Description 63
- Example Design 68
- Top Testbench 68
- Testbench Simulation Behavior 70
- Internal Serial Loopback Mode 72
- External Loopback Mode 72
- CRC32 Error Injection 78
- Advanced Parameter Settings 79
- Counter Reset Bits 80
- Include Temp Sense 80
- RXFIFO Address Width 80
- Use ATX or CMU PLL 82
- Lane Profile 82
- MegaCore Function 84
- Ethernet Traffic 89
- Additional Information 91
- How to Contact Altera 93
- Typographic Conventions 93
- Visual Cue Meaning 94
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