Altera 50G Interlaken MegaCore Function Manual de usuario Pagina 36

  • Descarga
  • Añadir a mis manuales
  • Imprimir
  • Pagina
    / 94
  • Tabla de contenidos
  • MARCADORES
  • Valorado. / 5. Basado en revisión del cliente
Vista de pagina 35
4'b1011 on itx_eopbits, to tell the IP core that in this clock cycle, the two most significant words of the
data symbol contain valid data and the remaining words do not contain valid data, and that in the second
of these two words, only the three most significant bytes contain valid data.
In Interleaved Mode, you can transfer a packet without interleaving as long as the channel number does
not toggle during the same packet transfer. However, you must still assert the itx_sob and itx_eob
signals correctly to maintain the proper burst boundaries.
If you do not drive the itx_sob and itx_eob signals, the 50G Interlaken IP Core does not operate
properly and the transmit FIFO may overflow, since in this mode the internal logic is looking for itx_sob
and itx_eob assertion for insertion of proper burst control words.
50G Interlaken IP Core Packet Mode Operation Example
Figure 4-5: Packet Transfer on Transmit Interface in Packet Mode
This example illustrates the expected behavior of the 50G Interlaken IP core application interface transmit
signals during a packet transfer in packet mode.
tx_usr_clk
itx_sop
itx_chan
itx_sob
itx_eob
itx_din_words
itx_num_valid
itx_eopbits
itx_ready
itx_calendar
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9
8’h2
d1
d2
d3
3’b100
3’b100
3’b011
4’b0000
4’b1011
64’hffff_ffff_ffff_ffff 64’h1111_2222_3333_4444
The figure illustrates a packet mode data transfer of 83 bytes on the transmit interface into the IP core. In
this mode, the 50G Interlaken IP core ignores the itx_sob and itx_eob input signals.
To start a transfer, you assert itx_sop when you have data ready on itx_din_words. At the following
rising edge of the clock, the IP core detects that itx_sop is asserted, indicating that the value on
itx_din_words in the current cycle is the start of an incoming data packet. When you assert itx_sop,
you must also assert the correct value on itx_chan to tell the IP core the data channel source of the data.
In this example, the value 2 on itx_chan tells the IP core that the data originates from channel number 2.
4-10
50G Interlaken IP Core Packet Mode Operation Example
UG-01140
2015.05.04
Altera Corporation
Functional Description
Send Feedback
Vista de pagina 35
1 2 ... 31 32 33 34 35 36 37 38 39 40 41 ... 93 94

Comentarios a estos manuales

Sin comentarios