Altera Stratix V Avalon-MM Interface for PCIe Solutions Manual de usuario Pagina 95
- Pagina / 184
- Tabla de contenidos
- MARCADORES
Valorado. / 5. Basado en revisión del cliente
Byte Offset
Register Dir Description
• 10011: Loopback.Exit
• 10100: Hot.Reset
• 10101: LOs
• 11001: L2.transmit.Wake
• 11010: Speed.Recovery
• 11011: Recovery.Equalization, Phase 0
• 11100: Recovery.Equalization, Phase 1
• 11101: Recovery.Equalization, Phase 2
• 11110: recovery.Equalization, Phase 3
14'h3C68 current_speed_reg[1:0]
O Indicates the current speed of the PCIe link. The
following encodings are defined:
• 2b’00: Undefined
• 2b’01: Gen1
• 2b’10: Gen2
• 2b’11: Gen3
14'h3C6C lane_act_reg[3:0]
O Lane Active Mode: This signal indicates the number
of lanes that configured during link training. The
following encodings are defined:
• 4’b0001: 1 lane
• 4’b0010: 2 lanes
• 4’b0100: 4 lanes
• 4’b1000: 8 lanes
Related Information
• PCI Express Base Specification 2.1 or 3.0
• PCI Local Bus Specification, Rev. 3.0
Programming Model for Avalon‑MM Root Port
The Application Layer writes the Root Port TLP TX Data registers with TLP formatted data for Configu‐
ration Read and Write Requests, Message TLPs, I/O Read and Write Requests, or single dword Memory
Read and Write Requests. Software should check the Root Port Link Status register (offset 0x92) to
ensure the Data Link Layer Link Active bit is set to 1'b1 before issuing a Configuration request to
downstream ports.
The Application Layer data must be in the appropriate TLP format with the data payload aligned to the
TLP address. Aligning the payload data to the TLP address may result in the payload data being either
aligned or unaligned to the qword. The following figure illustrates three dword TLPs with data that is
aligned and unaligned to the qword.
5-26
Programming Model for Avalon‑MM Root Port
UG-01097_avmm
2014.12.15
Altera Corporation
Registers
Send Feedback
- User Guide 1
- Datasheet 2
- Features 3
- Interface 4
- Release Information 7
- Device Family Support 7
- Altera FPGA 8
- Debug Features 10
- IP Core Verification 10
- Recommended Speed Grades 11
- Running Qsys 14
- Generating the Example Design 15
- Simulating Altera Designs 17
- Time TLP Type Payload 18
- TLP Header 18
- Creating a Quartus II Project 19
- Compiling the Design 19
- Programming a Device 20
- Parameter Settings 21
- Parameter Value Description 22
- Device Capabilities 25
- Error Reporting 26
- Link Capabilities 27
- MSI and MSI-X Capabilities 28
- Power Management 29
- Clock Domains on page 6-5 33
- Application Layer 34
- RX Avalon-MM Master Signals 36
- Clock Signals 41
- Signal Direction Description 42
- Variant Logical Interfaces 49
- Hard IP Status Extension 50
- Field and Bit Map 58
- 0134678951 58
- Bit(s) Field Description 59
- Serial Data Signals 60
- PIPE Interface Signals 64
- Test Signals 69
- Registers 70
- Altera-Defined VSEC Registers 78
- CvP Registers 79
- Address Range Register 83
- Bit Name Access Description 84
- Bits Name Access Description 85
- PCI Express Mailbox Registers 86
- Avalon-MM Mailbox Registers 90
- Address Name Access 91
- Description 91
- Byte Offset 91
- Register Dir Description 91
- Sending a Write TLP 97
- Root Port TLP Data Registers 99
- UG-01097_avmm 100
- 2014.12.15 100
- Related Information 101
- Bits Register Description 102
- Reset and Clocks 105
- Hard IP for PCI Express 106
- Example Design 106
- Clock Domains 109
- Data Rate Frequency 110
- Clock Summary 112
- Interrupts for Endpoints 113
- MSI/MSI‑X Support 115
- MsiIntfc_o[81:0] 116
- MsiControl_o[15:0] 116
- MsixIntfc_o[15:0] 116
- IntxReq_i 116
- IntxAck_o 116
- Error Handling 117
- Physical Layer Errors 118
- Data Link Layer Errors 118
- Transaction Layer Errors 119
- Error Type Description 120
- Status Bit Conditions 123
- IP Core Architecture 125
- Hard IP for PCI Express 126
- Top-Level Interfaces 127
- Avalon-MM Interface 127
- Clocks and Reset 127
- Transceiver Reconfiguration 127
- Interrupts 127
- Data Link Layer 128
- Altera Corporation 129
- Send Feedback 129
- Physical Layer 130
- TX Packets 131
- Avalon‑MM Bridge TLPs 135
- Byte Enable Value Description 136
- PCI Express Avalon-MM Bridge 138
- RX Block 144
- Avalon-MM RX Master Block 144
- TX Block 145
- Interrupt Handler Block 145
- Enable PLL calibration 147
- Throughput Optimization 151
- Throughput of Posted Writes 153
- Design Implementation 155
- CONF_DONE 156
- Endpoint Reset 156
- Root Port Reset 156
- SDC Timing Constraints 157
- Optional Features 159
- ECRC on the RX Path 160
- ECRC on the TX Path 161
- Debugging 163
- Setting Up Simulation 166
- Use Third-Party PCIe Analyzer 168
- BIOS Enumeration Issues 168
- Address[31:2] 169
- Figure A-6: I/O Read Request 171
- 7 6 5 4 3 2 1 0 175
- Core Config 8 4 1 175
- Additional Information 177
- Date Version Changes Made 178
- How to Contact Altera 182
- Typographic Conventions 182
- Visual Cue Meaning 183
Relacionado con productos y manuales para Instrumentos de medición Altera Stratix V Avalon-MM Interface for PCIe Solutions
Instrumentos de medición Altera 10-Gbps Ethernet MAC MegaCore Function Manual de usuario
(175 paginas)
(175 paginas)
Instrumentos de medición Altera Triple Speed Ethernet MegaCore Function Manual de usuario
(223 paginas)
(223 paginas)
Instrumentos de medición Altera 8B10B Encoder/Decoder MegaCore Function Manual de usuario
(32 paginas)
(32 paginas)
Instrumentos de medición Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core Manual de usuario
(11 paginas)
(11 paginas)
Instrumentos de medición Altera Embedded Systems Development Kit, Cyclone III Edit Manual de usuario
(82 paginas)
(82 paginas)
© 2020, manymanuals.es. Todos los derechos reservados | 0.040 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Comentarios a estos manuales