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Register Width Direction Description
cfg_tcvcmap
24 Output Configuration traffic class (TC)/virtual channel
(VC) mapping. The Application Layer uses this
signal to generate a TLP mapped to the appropriate
channel based on the traffic class of the packet.
• cfg_tcvcmap[2:0]: Mapping for TC0 (always 0)
.
• cfg_tcvcmap[5:3]: Mapping for TC1.
• cfg_tcvcmap[8:6]: Mapping for TC2.
• cfg_tcvcmap[11:9]: Mapping for TC3.
• cfg_tcvcmap[14:12]: Mapping for TC4.
• cfg_tcvcmap[17:15]: Mapping for TC5.
• cfg_tcvcmap[20:18]: Mapping for TC6.
• cfg_tcvcmap[23:21]: Mapping for TC7.
cfg_msi_data
16 Output cfg_msi_data[15:0] is message data for MSI.
cfg_busdev
13 Output Bus/Device Number captured by or programmed in
the Hard IP.
Figure 4-7: Configuration MSI Control Status Register
Field and Bit Map
0134678951
reserved
mask
capability
64-bit
address
capability
multiple message enable multiple message capable
MSI
enable
Table 4-13: Configuration MSI Control Status Register Field Descriptions
Bit(s) Field Description
[15:9] Reserved N/A
[8] mask capability Per-vector masking capable. This bit is hardwired to 0 because the
function does not support the optional MSI per-vector masking
using the Mask_Bits and Pending_Bits registers defined in the
PCI Local Bus Specification. Per-vector masking can be
implemented using Application Layer registers.
[7] 64-bit address
capability
64-bit address capable.
• 1: function capable of sending a 64-bit message address
• 0: function not capable of sending a 64-bit message address
UG-01097_avmm
2014.12.15
Configuration Space Register Access
4-25
64- or 128-Bit Avalon-MM Interface to the Application Layer
Altera Corporation
Send Feedback
- User Guide 1
- Datasheet 2
- Features 3
- Interface 4
- Release Information 7
- Device Family Support 7
- Altera FPGA 8
- Debug Features 10
- IP Core Verification 10
- Recommended Speed Grades 11
- Running Qsys 14
- Generating the Example Design 15
- Simulating Altera Designs 17
- Time TLP Type Payload 18
- TLP Header 18
- Creating a Quartus II Project 19
- Compiling the Design 19
- Programming a Device 20
- Parameter Settings 21
- Parameter Value Description 22
- Device Capabilities 25
- Error Reporting 26
- Link Capabilities 27
- MSI and MSI-X Capabilities 28
- Power Management 29
- Clock Domains on page 6-5 33
- Application Layer 34
- RX Avalon-MM Master Signals 36
- Clock Signals 41
- Signal Direction Description 42
- Variant Logical Interfaces 49
- Hard IP Status Extension 50
- Field and Bit Map 58
- 0134678951 58
- Bit(s) Field Description 59
- Serial Data Signals 60
- PIPE Interface Signals 64
- Test Signals 69
- Registers 70
- Altera-Defined VSEC Registers 78
- CvP Registers 79
- Address Range Register 83
- Bit Name Access Description 84
- Bits Name Access Description 85
- PCI Express Mailbox Registers 86
- Avalon-MM Mailbox Registers 90
- Address Name Access 91
- Description 91
- Byte Offset 91
- Register Dir Description 91
- Sending a Write TLP 97
- Root Port TLP Data Registers 99
- UG-01097_avmm 100
- 2014.12.15 100
- Related Information 101
- Bits Register Description 102
- Reset and Clocks 105
- Hard IP for PCI Express 106
- Example Design 106
- Clock Domains 109
- Data Rate Frequency 110
- Clock Summary 112
- Interrupts for Endpoints 113
- MSI/MSI‑X Support 115
- MsiIntfc_o[81:0] 116
- MsiControl_o[15:0] 116
- MsixIntfc_o[15:0] 116
- IntxReq_i 116
- IntxAck_o 116
- Error Handling 117
- Physical Layer Errors 118
- Data Link Layer Errors 118
- Transaction Layer Errors 119
- Error Type Description 120
- Status Bit Conditions 123
- IP Core Architecture 125
- Hard IP for PCI Express 126
- Top-Level Interfaces 127
- Avalon-MM Interface 127
- Clocks and Reset 127
- Transceiver Reconfiguration 127
- Interrupts 127
- Data Link Layer 128
- Altera Corporation 129
- Send Feedback 129
- Physical Layer 130
- TX Packets 131
- Avalon‑MM Bridge TLPs 135
- Byte Enable Value Description 136
- PCI Express Avalon-MM Bridge 138
- RX Block 144
- Avalon-MM RX Master Block 144
- TX Block 145
- Interrupt Handler Block 145
- Enable PLL calibration 147
- Throughput Optimization 151
- Throughput of Posted Writes 153
- Design Implementation 155
- CONF_DONE 156
- Endpoint Reset 156
- Root Port Reset 156
- SDC Timing Constraints 157
- Optional Features 159
- ECRC on the RX Path 160
- ECRC on the TX Path 161
- Debugging 163
- Setting Up Simulation 166
- Use Third-Party PCIe Analyzer 168
- BIOS Enumeration Issues 168
- Address[31:2] 169
- Figure A-6: I/O Read Request 171
- 7 6 5 4 3 2 1 0 175
- Core Config 8 4 1 175
- Additional Information 177
- Date Version Changes Made 178
- How to Contact Altera 182
- Typographic Conventions 182
- Visual Cue Meaning 183
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