Altera Stratix V Avalon-MM Interface for PCIe Solutions Manual de usuario Pagina 90
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Table 5-20: INT‑X Interrupt Enable Register for Endpoints, 0x3070
Bits Name Access Description
[31:0]
PCI Express to Avalon-MM
Interrupt Enable
RW When set to 1, enables the interrupt for
the corresponding bit in the PCI
Express to Avalon MM Interrupt
Status register to cause the Avalon
Interrupt signal (cra_Irq_o) to be
asserted.
Only bits implemented in the PCI
Express to Avalon MM Interrupt
Status register are implemented in the
Enable register. Reserved bits cannot be
set to a 1.
Avalon-MM Mailbox Registers
A processor local to the interconnect fabric typically requires write access to a set of Avalon-MM-to-PCI
Express Mailbox registers and read-only access to a set of PCI Express-to-Avalon-MM Mailbox
registers. Eight mailbox registers are available.
The Avalon-MM-to-PCI Express Mailbox registers are writable at the addresses shown in the following
table. When the Avalon-MM processor writes to one of these registers the corresponding bit in the
Avalon MM to PCI Express Interrupt Status register is set to 1.
Table 5-21: Avalon-MM to PCI Express Mailbox Registers, 0x3A00–0x3A1F
Address Name Access Description
0x3A00
A2P_MAILBOX0
RW Avalon-MM-to-PCI Express mailbox 0
0x3A04
A2P_MAILBOX1
RW Avalon-MM-to-PCI Express mailbox 1
0x3A08
A2P _MAILBOX2
RW Avalon-MM-to-PCI Express mailbox 2
0x3A0C
A2P _MAILBOX3
RW Avalon-MM-to-PCI Express mailbox 3
0x3A10
A2P _MAILBOX4
RW Avalon-MM-to-PCI Express mailbox 4
0x3A14
A2P _MAILBOX5
RW Avalon-MM-to-PCI Express mailbox 5
0x3A18
A2P _MAILBOX6
RW Avalon-MM-to-PCI Express mailbox 6
0x3A1C
A2P_MAILBOX7
RW Avalon-MM-to-PCI Express mailbox 7
UG-01097_avmm
2014.12.15
Avalon-MM Mailbox Registers
5-21
Registers
Altera Corporation
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- User Guide 1
- Datasheet 2
- Features 3
- Interface 4
- Release Information 7
- Device Family Support 7
- Altera FPGA 8
- Debug Features 10
- IP Core Verification 10
- Recommended Speed Grades 11
- Running Qsys 14
- Generating the Example Design 15
- Simulating Altera Designs 17
- Time TLP Type Payload 18
- TLP Header 18
- Creating a Quartus II Project 19
- Compiling the Design 19
- Programming a Device 20
- Parameter Settings 21
- Parameter Value Description 22
- Device Capabilities 25
- Error Reporting 26
- Link Capabilities 27
- MSI and MSI-X Capabilities 28
- Power Management 29
- Clock Domains on page 6-5 33
- Application Layer 34
- RX Avalon-MM Master Signals 36
- Clock Signals 41
- Signal Direction Description 42
- Variant Logical Interfaces 49
- Hard IP Status Extension 50
- Field and Bit Map 58
- 0134678951 58
- Bit(s) Field Description 59
- Serial Data Signals 60
- PIPE Interface Signals 64
- Test Signals 69
- Registers 70
- Altera-Defined VSEC Registers 78
- CvP Registers 79
- Address Range Register 83
- Bit Name Access Description 84
- Bits Name Access Description 85
- PCI Express Mailbox Registers 86
- Avalon-MM Mailbox Registers 90
- Address Name Access 91
- Description 91
- Byte Offset 91
- Register Dir Description 91
- Sending a Write TLP 97
- Root Port TLP Data Registers 99
- UG-01097_avmm 100
- 2014.12.15 100
- Related Information 101
- Bits Register Description 102
- Reset and Clocks 105
- Hard IP for PCI Express 106
- Example Design 106
- Clock Domains 109
- Data Rate Frequency 110
- Clock Summary 112
- Interrupts for Endpoints 113
- MSI/MSI‑X Support 115
- MsiIntfc_o[81:0] 116
- MsiControl_o[15:0] 116
- MsixIntfc_o[15:0] 116
- IntxReq_i 116
- IntxAck_o 116
- Error Handling 117
- Physical Layer Errors 118
- Data Link Layer Errors 118
- Transaction Layer Errors 119
- Error Type Description 120
- Status Bit Conditions 123
- IP Core Architecture 125
- Hard IP for PCI Express 126
- Top-Level Interfaces 127
- Avalon-MM Interface 127
- Clocks and Reset 127
- Transceiver Reconfiguration 127
- Interrupts 127
- Data Link Layer 128
- Altera Corporation 129
- Send Feedback 129
- Physical Layer 130
- TX Packets 131
- Avalon‑MM Bridge TLPs 135
- Byte Enable Value Description 136
- PCI Express Avalon-MM Bridge 138
- RX Block 144
- Avalon-MM RX Master Block 144
- TX Block 145
- Interrupt Handler Block 145
- Enable PLL calibration 147
- Throughput Optimization 151
- Throughput of Posted Writes 153
- Design Implementation 155
- CONF_DONE 156
- Endpoint Reset 156
- Root Port Reset 156
- SDC Timing Constraints 157
- Optional Features 159
- ECRC on the RX Path 160
- ECRC on the TX Path 161
- Debugging 163
- Setting Up Simulation 166
- Use Third-Party PCIe Analyzer 168
- BIOS Enumeration Issues 168
- Address[31:2] 169
- Figure A-6: I/O Read Request 171
- 7 6 5 4 3 2 1 0 175
- Core Config 8 4 1 175
- Additional Information 177
- Date Version Changes Made 178
- How to Contact Altera 182
- Typographic Conventions 182
- Visual Cue Meaning 183
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