Altera Stratix V Avalon-MM Interface for PCIe Solutions Manual de usuario Pagina 35
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Figure 4-1: 64- or 128-Bit Avalon-MM Interface to the Application Layer
tx_out0[<n>:0]
rx_in0[<n>:0]
1-Bit Serial
cra_readdata[31:0]
cra_waitrequest
cra_byteenable[3:0]
cra_chipselect
cra_address[11:0]
cra_read
cra_write
cra_writedata[31:0]
txs_writedata[<w>-1:0]
txs_busrtcount[6:0]
txs_chipselect
txs_read
txs_write
txs_address[<w>-1:0]
txs_byteenable[7:0]
txs_readdatavalid
txs_readdata[<w>-1:0]
txs_waitrequest
32-Bit
Avalon-MM
CRA
Slave Port
(Optional,
Not available for
Completer-Only
Single Dword)
64- or 128-Bit
Avalon-MM TX
Slave Port
(Not used for
Completer-Only)
Test
Interface
test_in[31:0]
simu_mode_pipe
rxm_bar0_write_<n>
rxm_bar0_address_<n>[31:0]
rxm_bar0_writedata_<n>[63:0] or [31:0]
rxm_bar0_byteenable_<n>[7:0]
rxm_bar0_burstcount_<n>[6:0]
rxm_bar0_waitrequest_<n>
rxm_bar0_read_<n>
rxm_bar0_readdata_<n>[63:0]
rxm_bar0_readdatavalid
rxm_irq[<m>:0], <m> < 16
reconfig_from_xcvr[<n>46-1:0]
MsiIntfc_o[81:0]
MsiControl_o[15:0]
MsixIntfc_o[15:0]
IntxReq_i
IntxAck_o
reconfig_to_xcvr[<n>70-1:0]
Transceiver
Multiple
MSI/MSI-X
Hard IP
Status
Extension
Reconfiguration
Clocks
npor
nreset_status
pin_perst
cfg_par_err
derr_cor_ext_rcv
derr_ext_rpl
derr_rpl
dlup
dlup_exit
ev128ns
ev1us
hotrst_exit
int_status[3:0]
ko_cpl_spc_data[11:0]
ko_cpl_spc_header[7:0]
l2_ext
lane_act[3:0]
ltssmstate[4:0]
rx_par_err
tx_par_err
Reset &
Lock Status
refclk
coreclkout
cra_irq_irq
txdata0[7:0]
txdatak0
txblkst0
rxdata0[7:0]
rxdatak0
rxblkst0
txdetectrx0
txelecidle0
txcompl0
rxpolarity0
powerdown0[1:0]
currentcoeff0[17:0]
currentrxpreset0[2:0]
txmargin[2:0]
txswing
txsynchd0[1:0]
rxsyncd[1:0]
rxvalid0
phystatus0
rxelecidle0
rxstatus0[2:0]
simu_mode_pipe
sim_pipe_rate[1:0]
sim_pipe_pclk_in
sim_pipe_pclk_out
sim_pipe_clk250_out
sim_pipe_clk500_out
sim_ltssmstate[4:0]
rxfreqlocked0
rxdataskip0
eidleinfersel0[2:0]
txdeemph0
Transmit Data
Interface Signals
Receive Data
Interface Signals
Command
Interface Signals
Status
Interface Signals
64- or 128-Bit Avalon-MM Intearface to
Application Layer
PIPE
Interface
for Simulation
and Hardware
Debug Using
dl_ltssm[4:0]
SignalTap,
Gen3 version
pld_clk_inuse
pme_to_sr
rx_st_bar[7:0]
rx_st_data[127:0]
rx_st_eop
rx_st_err
rx_st_sop
rx_st_valid
serr_out
tl_cfg_add[3:0]
tx_cfg_sts[52:0]
tx_st_ready
Hard IP Reset,
Status and
Link Training
64-Bit
Avalon-MM RX
BAR Master Port
Note: Signals listed for BAR0 are the same as those for BAR1–BAR5 when those BARs are enabled in the
parameter editor.
Variations using the Avalon-MM interface implement the Avalon-MM protocol described in the Avalon
Interface Specifications. Refer to this specification for information about the Avalon-MM protocol,
including timing diagrams.
Related Information
Avalon Interface Specifications
4-2
64- or 128-Bit Avalon-MM Interface to the Application Layer
UG-01097_avmm
2014.12.15
Altera Corporation
64- or 128-Bit Avalon-MM Interface to the Application Layer
Send Feedback
- User Guide 1
- Datasheet 2
- Features 3
- Interface 4
- Release Information 7
- Device Family Support 7
- Altera FPGA 8
- Debug Features 10
- IP Core Verification 10
- Recommended Speed Grades 11
- Running Qsys 14
- Generating the Example Design 15
- Simulating Altera Designs 17
- Time TLP Type Payload 18
- TLP Header 18
- Creating a Quartus II Project 19
- Compiling the Design 19
- Programming a Device 20
- Parameter Settings 21
- Parameter Value Description 22
- Device Capabilities 25
- Error Reporting 26
- Link Capabilities 27
- MSI and MSI-X Capabilities 28
- Power Management 29
- Clock Domains on page 6-5 33
- Application Layer 34
- RX Avalon-MM Master Signals 36
- Clock Signals 41
- Signal Direction Description 42
- Variant Logical Interfaces 49
- Hard IP Status Extension 50
- Field and Bit Map 58
- 0134678951 58
- Bit(s) Field Description 59
- Serial Data Signals 60
- PIPE Interface Signals 64
- Test Signals 69
- Registers 70
- Altera-Defined VSEC Registers 78
- CvP Registers 79
- Address Range Register 83
- Bit Name Access Description 84
- Bits Name Access Description 85
- PCI Express Mailbox Registers 86
- Avalon-MM Mailbox Registers 90
- Address Name Access 91
- Description 91
- Byte Offset 91
- Register Dir Description 91
- Sending a Write TLP 97
- Root Port TLP Data Registers 99
- UG-01097_avmm 100
- 2014.12.15 100
- Related Information 101
- Bits Register Description 102
- Reset and Clocks 105
- Hard IP for PCI Express 106
- Example Design 106
- Clock Domains 109
- Data Rate Frequency 110
- Clock Summary 112
- Interrupts for Endpoints 113
- MSI/MSI‑X Support 115
- MsiIntfc_o[81:0] 116
- MsiControl_o[15:0] 116
- MsixIntfc_o[15:0] 116
- IntxReq_i 116
- IntxAck_o 116
- Error Handling 117
- Physical Layer Errors 118
- Data Link Layer Errors 118
- Transaction Layer Errors 119
- Error Type Description 120
- Status Bit Conditions 123
- IP Core Architecture 125
- Hard IP for PCI Express 126
- Top-Level Interfaces 127
- Avalon-MM Interface 127
- Clocks and Reset 127
- Transceiver Reconfiguration 127
- Interrupts 127
- Data Link Layer 128
- Altera Corporation 129
- Send Feedback 129
- Physical Layer 130
- TX Packets 131
- Avalon‑MM Bridge TLPs 135
- Byte Enable Value Description 136
- PCI Express Avalon-MM Bridge 138
- RX Block 144
- Avalon-MM RX Master Block 144
- TX Block 145
- Interrupt Handler Block 145
- Enable PLL calibration 147
- Throughput Optimization 151
- Throughput of Posted Writes 153
- Design Implementation 155
- CONF_DONE 156
- Endpoint Reset 156
- Root Port Reset 156
- SDC Timing Constraints 157
- Optional Features 159
- ECRC on the RX Path 160
- ECRC on the TX Path 161
- Debugging 163
- Setting Up Simulation 166
- Use Third-Party PCIe Analyzer 168
- BIOS Enumeration Issues 168
- Address[31:2] 169
- Figure A-6: I/O Read Request 171
- 7 6 5 4 3 2 1 0 175
- Core Config 8 4 1 175
- Additional Information 177
- Date Version Changes Made 178
- How to Contact Altera 182
- Typographic Conventions 182
- Visual Cue Meaning 183
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