Altera Stratix V Avalon-MM Interface for PCIe Solutions Manual de usuario Pagina 143
- Pagina / 184
- Tabla de contenidos
- MARCADORES
Valorado. / 5. Basado en revisión del cliente
Figure 9-10: Avalon-MM-to-PCI Express Address Translation
The following figure depicts the Avalon-MM-to-PCI Express address translation process. In this figure
the variables represent the following paramers:
• N—the number of pass-through bits.
• M—the number of Avalon-MM address bits.
• P—the number of PCIe address bits.
• Q—the number of translation table entries.
• Sp[1:0]—the space indication for each entry.
PCIe Address Q-1
SpQ-1
Space Indication
PCI Express address from Table Entry
becomes High PCI Express address bits
PCI Express Address
High
Low
P-1 N N-1 0
Low address bits unchanged
Avalon-MM-to-PCI Express
Address Translation Table
(Q entries by P-N bits wide)
PCIe Address 0 Sp0
PCIe Address 1 Sp1
Avalon-MM Address
High
Slave Base
Address
Low
M-131 M N N-1 0
Table updates from
control register port
High Avalon-MM Address
Bits Index table
Completer Only Single Dword Endpoint
The completer only single dword endpoint is intended for applications that use the PCI Express protocol
to perform simple read and write register accesses from a host CPU. The completer only single dword
endpoint is a hard IP implementation available for Qsys systems, and includes an Avalon-MM interface to
the Application Layer. The Avalon-MM interface connection in this variation is 32 bits wide. This
endpoint is not pipelined; at any time a single request can be outstanding.
The completer-only single dword endpoint supports the following requests:
• Read and write requests of a single dword (32 bits) from the Root Complex
• Completion with Completer Abort status generation for other types of non-posted requests
• INTX or MSI support with one Avalon-MM interrupt source
UG-01097_avmm
2014.12.15
Completer Only Single Dword Endpoint
9-19
IP Core Architecture
Altera Corporation
Send Feedback
- User Guide 1
- Datasheet 2
- Features 3
- Interface 4
- Release Information 7
- Device Family Support 7
- Altera FPGA 8
- Debug Features 10
- IP Core Verification 10
- Recommended Speed Grades 11
- Running Qsys 14
- Generating the Example Design 15
- Simulating Altera Designs 17
- Time TLP Type Payload 18
- TLP Header 18
- Creating a Quartus II Project 19
- Compiling the Design 19
- Programming a Device 20
- Parameter Settings 21
- Parameter Value Description 22
- Device Capabilities 25
- Error Reporting 26
- Link Capabilities 27
- MSI and MSI-X Capabilities 28
- Power Management 29
- Clock Domains on page 6-5 33
- Application Layer 34
- RX Avalon-MM Master Signals 36
- Clock Signals 41
- Signal Direction Description 42
- Variant Logical Interfaces 49
- Hard IP Status Extension 50
- Field and Bit Map 58
- 0134678951 58
- Bit(s) Field Description 59
- Serial Data Signals 60
- PIPE Interface Signals 64
- Test Signals 69
- Registers 70
- Altera-Defined VSEC Registers 78
- CvP Registers 79
- Address Range Register 83
- Bit Name Access Description 84
- Bits Name Access Description 85
- PCI Express Mailbox Registers 86
- Avalon-MM Mailbox Registers 90
- Address Name Access 91
- Description 91
- Byte Offset 91
- Register Dir Description 91
- Sending a Write TLP 97
- Root Port TLP Data Registers 99
- UG-01097_avmm 100
- 2014.12.15 100
- Related Information 101
- Bits Register Description 102
- Reset and Clocks 105
- Hard IP for PCI Express 106
- Example Design 106
- Clock Domains 109
- Data Rate Frequency 110
- Clock Summary 112
- Interrupts for Endpoints 113
- MSI/MSI‑X Support 115
- MsiIntfc_o[81:0] 116
- MsiControl_o[15:0] 116
- MsixIntfc_o[15:0] 116
- IntxReq_i 116
- IntxAck_o 116
- Error Handling 117
- Physical Layer Errors 118
- Data Link Layer Errors 118
- Transaction Layer Errors 119
- Error Type Description 120
- Status Bit Conditions 123
- IP Core Architecture 125
- Hard IP for PCI Express 126
- Top-Level Interfaces 127
- Avalon-MM Interface 127
- Clocks and Reset 127
- Transceiver Reconfiguration 127
- Interrupts 127
- Data Link Layer 128
- Altera Corporation 129
- Send Feedback 129
- Physical Layer 130
- TX Packets 131
- Avalon‑MM Bridge TLPs 135
- Byte Enable Value Description 136
- PCI Express Avalon-MM Bridge 138
- RX Block 144
- Avalon-MM RX Master Block 144
- TX Block 145
- Interrupt Handler Block 145
- Enable PLL calibration 147
- Throughput Optimization 151
- Throughput of Posted Writes 153
- Design Implementation 155
- CONF_DONE 156
- Endpoint Reset 156
- Root Port Reset 156
- SDC Timing Constraints 157
- Optional Features 159
- ECRC on the RX Path 160
- ECRC on the TX Path 161
- Debugging 163
- Setting Up Simulation 166
- Use Third-Party PCIe Analyzer 168
- BIOS Enumeration Issues 168
- Address[31:2] 169
- Figure A-6: I/O Read Request 171
- 7 6 5 4 3 2 1 0 175
- Core Config 8 4 1 175
- Additional Information 177
- Date Version Changes Made 178
- How to Contact Altera 182
- Typographic Conventions 182
- Visual Cue Meaning 183
Relacionado con productos y manuales para Instrumentos de medición Altera Stratix V Avalon-MM Interface for PCIe Solutions
Instrumentos de medición Altera 10-Gbps Ethernet MAC MegaCore Function Manual de usuario
(175 paginas)
(175 paginas)
Instrumentos de medición Altera Triple Speed Ethernet MegaCore Function Manual de usuario
(223 paginas)
(223 paginas)
Instrumentos de medición Altera 8B10B Encoder/Decoder MegaCore Function Manual de usuario
(32 paginas)
(32 paginas)
Instrumentos de medición Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core Manual de usuario
(11 paginas)
(11 paginas)
Instrumentos de medición Altera Embedded Systems Development Kit, Cyclone III Edit Manual de usuario
(82 paginas)
(82 paginas)
© 2020, manymanuals.es. Todos los derechos reservados | 0.051 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Comentarios a estos manuales