Altera POS-PHY Level 4 IP Core Manual de usuario Pagina 94
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5–24 Chapter 5: Functional Description—Transmitter
Avalon-MM Interface Register Map
POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation
Avalon-MM Interface Register Map
Table 5–10 lists the Avalon-MM interface registers.
Table 5–9. Scheduler Control and Status
Signal Direction Clock Domain Description
ctl_td_mb1[10:0]
Input
tdint_clk
Maximum number of bytes that can be transmitted when the
downstream FIFO buffer is starving. This number does not
imply that a control word is inserted. Units are in bytes.
Supports 0 to 2,032 bytes in 16-byte increments. This port is
absent if you turn on Shared Buffer with Embedded
Addressing.
ctl_td_mb2[10:0]
Input
Maximum number of bytes that can be transmitted when the
downstream FIFO buffer is hungry. This number does not
imply that a control word is inserted. Units are in bytes.
Supports 0 to 2,032 bytes in 16-byte increments. This port is
absent if you turn on Shared Buffer with Embedded
Addressing.
ctl_td_
switchmode[1:0]
Input -
Static reset
This input determines the port switching behavior of the
scheduler.
■ The scheduler always makes a port switch decision when
ctl_td_burstlen
data is sent, or when an EOP is sent.
■ Next credits are held in a table for all ports, and are
incremented by status updates.
■ Current credits are stored in a separate register for a single
port while it is serviced, and become stale because status
updates do not increment the value.
■ A port is only eligible for scheduling if there are greater
than or equal to
ctl_td_burstlen
next credits available,
and greater than or equal to
ctl_td_burstlen
data
available in the corresponding Atlantic FIFO buffer.
■ When ‘00’ (switch on EOP is turned off) the scheduler
switches when less than
ctl_td_burstlen
current
credits are available, or less than
ctl_td_burstlen
data
is available in the Atlantic buffer.
■ When ‘01’ (switch on EOP is turned on), the scheduler
switches when less than
ctl_td_burstlen
current
credits are available, or less than
ctl_td_burstlen
data
is available in the Atlantic buffer, or an EOP is sent.
■ When ‘10’ or ‘11’, the scheduler switches when
ctl_td_burstlen
data is sent, or an EOP is sent.
■ In the IP Toolbench top-level file, the upper bit is always
tied to zero, and the lower bit is tied depending on the value
of the switch on end of packet feature. This port is absent if
you turn on Shared Buffer with Embedded Addressing.
Only change at reset.
- User Guide 1
- POS-PHY Level 4 IP Core 1
- 1. About This IP Core 3
- General Description 5
- Interfaces & Protocols 6
- IP Core Verification 7
- OpenCore Plus IP Evaluation 9
- 2. Getting Started 11
- Using the Parameter Editor 12
- Upgrading Outdated IP Cores 13
- Specify Parameters 15
- Simulate the Design 17
- 3. Parameter Settings 21
- LVDS Data Rate 22
- PLL Input Frequency 23
- Data Path Width 23
- Buffer Mode 23
- Basic Parameters 24
- Atlantic FIFO Buffer Clock 25
- Atlantic Interface Width 25
- Optional Features 26
- Transmitter Options 27
- Receiver Options 28
- Starving Starving Starving 29
- Starving Hungry Hungry 29
- Starving Satisfied Satisfied 29
- FIFO RAM Blocks 30
- Note to Table 3–5: 31
- Protocol Parameters 32
- Features 39
- Block Description 39
- ALTLVDS_RX IP Core 41
- Data Processor (rx_data_proc) 42
- Atlantic Buffers 43
- Individual Buffers 44
- Status Processor 45
- Notes to Figure 4–3: 46
- Note to Table 4–1: 47
- Notes to Figure 4–4: 48
- Requirements for rxsys_clk 49
- Reset Structure 50
- Error Flagging and Handling 50
- SPI-4.2 Protocol Errors 51
- Notes to Table 4–3: 53
- DIP-4 Marking 54
- Notes to Figure 4–8: 56
- Missing SOP 59
- Missing EOP 60
- Note to Table 4–7: 62
- Note to Table 4–8: 63
- Note to Table 4–9: 63
- Latency Information 68
- Data Processor (tx_data_proc) 74
- Status Bypass Port 77
- Clock Structure 78
- Multiple Clock Domain 79
- Notes to Figure 5–4: 80
- Note to Table 5–5: 88
- 6. Testbench 99
- Variation 100
- Receiver 100
- Receiver Testbench Examples 101
- 6–4 Chapter 6: Testbench 102
- Chapter 6: Testbench 6–5 103
- 6–6 Chapter 6: Testbench 104
- Chapter 6: Testbench 6–7 105
- 6–8 Chapter 6: Testbench 106
- A. Start-Up Sequence 107
- Troubleshooting 109
- Issues and Tips—Miscellaneous 111
- Separate PLLs 113
- Shared PLL 113
- "<rx_pll>" 114
- Note to Table C–1: 115
- D. Board Design 117
- Probe Points 118
- Spare Pins 119
- JTAG Scan Chain 119
- D–4 Appendix D: Board Design 120
- Design for Testability 120
- Introduction 121
- Static Alignment 125
- Dynamic Alignment 126
- Altera Solutions 126
- Dynamic Phase Alignment (DPA) 127
- AC Timing Analysis 128
- Budgets 129
- G. Conversion from v2.2.x 131
- Receiver Signals 132
- Transmitter Signals 134
- Additional Information 139
- Note to Table: 140
- Additional Information Info–3 141
- Typographic Conventions 141
- Info–4 Additional Information 142
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