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5–6 Chapter 5: Functional Description—Transmitter
Block Description
POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation
For 32-bit (quarter-rate) variations, an ALTDDIO IP core serializes the
tdclk
,
tdat
,
and
tctl
lines.
Status Processor
The transmitter IP core monitors and decodes the
tstat
status channel from the
receiver. It handles framing, checking for DIP-2 errors, and extracting status. The
status is provided to the transmit scheduler if present, and is always available to the
user logic. The clock edge on which the transmitter samples the status channel is
programmable.
The re-timed optimistic/pessimistic filtered status appears on the following signals:
■
ctl_ty_extstat_val
: asserted when the following two signals are valid
■
ctl_ty_extstat_adr
: port
■
ctl_ty_extstat
: status
These signals are synchronous with the positive edge of
txsys_clk.
The
txsys_clk
must be faster than the status clock,
tsclk
.
Based on the received status channel, these signals are updated when the finite state
machine is not in disable state. It is up to the user logic to ensure these signals are
used when
stat_ts_sync
is asserted.
In the individual buffers mode, if these signals are not connected to the user logic, the
Quartus II software removes the status FIFO buffer (
tx_stat_fifo_user
).
Given a calendar slot number, the status processor determines which port's status
belongs in the slot according to the calendar that it stores. When Asymmetric Port
Support is turned off, the port number corresponds with the slot number (that is, slot
one is port one, and so on). When Asymmetric Port Support is turned on, a
programmable calendar is stored in memory, and the port corresponding to the slot is
looked up.
1 If the Asymmetric Port Support parameter is turned on, the Avalon
®
Memory-
Mapped (Avalon-MM) registers must be programmed prior to releasing the
rsfrm
bit
(refer to Appendix E and the “Avalon-MM Interface Register Map” on page 5–24).
Figure 5–2. Transmitter Timing Diagram
Note to Figure 5–2:
(1)
val
is negated when the internal status FIFO buffer empties.
txsys_clk
stat_ty_extstat
stat_ty_extstat_val
stat_ty_extstat_adr
2'b00 2'b00 2'b00 2'b00 2'b01 2'bxx 2'bxx 2'bxx 2'b01 2'b00 2'b10
8'd0 8'd1 8'd2 8'd3 8'd4 8'dx 8'dx 8'dx 8'd5 8'd6 8'd7
2'b10
8'd0
- User Guide 1
- POS-PHY Level 4 IP Core 1
- 1. About This IP Core 3
- General Description 5
- Interfaces & Protocols 6
- IP Core Verification 7
- OpenCore Plus IP Evaluation 9
- 2. Getting Started 11
- Using the Parameter Editor 12
- Upgrading Outdated IP Cores 13
- Specify Parameters 15
- Simulate the Design 17
- 3. Parameter Settings 21
- LVDS Data Rate 22
- PLL Input Frequency 23
- Data Path Width 23
- Buffer Mode 23
- Basic Parameters 24
- Atlantic FIFO Buffer Clock 25
- Atlantic Interface Width 25
- Optional Features 26
- Transmitter Options 27
- Receiver Options 28
- Starving Starving Starving 29
- Starving Hungry Hungry 29
- Starving Satisfied Satisfied 29
- FIFO RAM Blocks 30
- Note to Table 3–5: 31
- Protocol Parameters 32
- Features 39
- Block Description 39
- ALTLVDS_RX IP Core 41
- Data Processor (rx_data_proc) 42
- Atlantic Buffers 43
- Individual Buffers 44
- Status Processor 45
- Notes to Figure 4–3: 46
- Note to Table 4–1: 47
- Notes to Figure 4–4: 48
- Requirements for rxsys_clk 49
- Reset Structure 50
- Error Flagging and Handling 50
- SPI-4.2 Protocol Errors 51
- Notes to Table 4–3: 53
- DIP-4 Marking 54
- Notes to Figure 4–8: 56
- Missing SOP 59
- Missing EOP 60
- Note to Table 4–7: 62
- Note to Table 4–8: 63
- Note to Table 4–9: 63
- Latency Information 68
- Data Processor (tx_data_proc) 74
- Status Bypass Port 77
- Clock Structure 78
- Multiple Clock Domain 79
- Notes to Figure 5–4: 80
- Note to Table 5–5: 88
- 6. Testbench 99
- Variation 100
- Receiver 100
- Receiver Testbench Examples 101
- 6–4 Chapter 6: Testbench 102
- Chapter 6: Testbench 6–5 103
- 6–6 Chapter 6: Testbench 104
- Chapter 6: Testbench 6–7 105
- 6–8 Chapter 6: Testbench 106
- A. Start-Up Sequence 107
- Troubleshooting 109
- Issues and Tips—Miscellaneous 111
- Separate PLLs 113
- Shared PLL 113
- "<rx_pll>" 114
- Note to Table C–1: 115
- D. Board Design 117
- Probe Points 118
- Spare Pins 119
- JTAG Scan Chain 119
- D–4 Appendix D: Board Design 120
- Design for Testability 120
- Introduction 121
- Static Alignment 125
- Dynamic Alignment 126
- Altera Solutions 126
- Dynamic Phase Alignment (DPA) 127
- AC Timing Analysis 128
- Budgets 129
- G. Conversion from v2.2.x 131
- Receiver Signals 132
- Transmitter Signals 134
- Additional Information 139
- Note to Table: 140
- Additional Information Info–3 141
- Typographic Conventions 141
- Info–4 Additional Information 142
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