Altera POS-PHY Level 4 IP Core Manual de usuario Pagina 8
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1–6 Chapter 1: About This IP Core
Performance and Resource Utilization
POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation
Table 1–4. Performance—Shared Buffer With Embedded Addressing Mode—Stratix IV Devices
Parameters
ALUTs
Logic
Registers
Memory
Blocks
(M9K)
clk
f
MAX
(MHz)
Data Flow
Direction
Data Path
Width (bits)
Number of
Ports
EP4SGX70
DF29C3
EP4SGX230
DF29C3ES
Receiver
32 1 1,190 1,294 6 204 195
64 1 1,387 1,820 16 261 284
128 1 2,215 2,741 30 186 207
32 4 1,198 1,300 6 199 156
64 4 1,398 1,826 16 273 273
128 4 2,221 2,742 30 195 195
32 10 1,138 1,249 7 213 163
64 10 1,396 1,782 18 281 270
128 10 2,273 2,709 33 187 160
Transmitter
32 4 1,049 1,085 5 192 185
64 4 1,032 1,454 9 262 232
128 4 1,178 1,464 17 175 181
32 10 1,023 1,119 5 178 163
64 10 1,057 1,601 9 260 225
128 10 1,331 1,770 17 190 166
Table 1–5. Performance—Individual Buffers Mode—Stratix IV Devices
Parameters
ALUTs
Logic
Registers
Memory
Blocks
(M9K)
clk
f
MAX
(MHz)
Data Flow
Direction
Data Path
Width (bits)
Number of
Ports
EP4SGX70
DF29C3
EP4SGX230
DF29C3ES
Receiver
32 4 2,245 2,427 21 182 159
64 4 2,514 2,800 40 270 268
128 4 3,833 4,160 78 165 149
32 10 4,070 4,529 45 140 144
64 10 4,823 4,830 88 255 254
Transmitter
32 1 1,155 1,213 6 165 176
64 1 1,309 1,784 10 245 182
128 1 1,710 2,245 18 177 171
32 4 2,563 2,524 18 130 151
64 4 2,726 2,997 34 183 212
128 4 3,430 3,778 66 166 153
32 10 5,210 4,789 42 120 118
64 10 5,733 5,188 82 153 213
- User Guide 1
- POS-PHY Level 4 IP Core 1
- 1. About This IP Core 3
- General Description 5
- Interfaces & Protocols 6
- IP Core Verification 7
- OpenCore Plus IP Evaluation 9
- 2. Getting Started 11
- Using the Parameter Editor 12
- Upgrading Outdated IP Cores 13
- Specify Parameters 15
- Simulate the Design 17
- 3. Parameter Settings 21
- LVDS Data Rate 22
- PLL Input Frequency 23
- Data Path Width 23
- Buffer Mode 23
- Basic Parameters 24
- Atlantic FIFO Buffer Clock 25
- Atlantic Interface Width 25
- Optional Features 26
- Transmitter Options 27
- Receiver Options 28
- Starving Starving Starving 29
- Starving Hungry Hungry 29
- Starving Satisfied Satisfied 29
- FIFO RAM Blocks 30
- Note to Table 3–5: 31
- Protocol Parameters 32
- Features 39
- Block Description 39
- ALTLVDS_RX IP Core 41
- Data Processor (rx_data_proc) 42
- Atlantic Buffers 43
- Individual Buffers 44
- Status Processor 45
- Notes to Figure 4–3: 46
- Note to Table 4–1: 47
- Notes to Figure 4–4: 48
- Requirements for rxsys_clk 49
- Reset Structure 50
- Error Flagging and Handling 50
- SPI-4.2 Protocol Errors 51
- Notes to Table 4–3: 53
- DIP-4 Marking 54
- Notes to Figure 4–8: 56
- Missing SOP 59
- Missing EOP 60
- Note to Table 4–7: 62
- Note to Table 4–8: 63
- Note to Table 4–9: 63
- Latency Information 68
- Data Processor (tx_data_proc) 74
- Status Bypass Port 77
- Clock Structure 78
- Multiple Clock Domain 79
- Notes to Figure 5–4: 80
- Note to Table 5–5: 88
- 6. Testbench 99
- Variation 100
- Receiver 100
- Receiver Testbench Examples 101
- 6–4 Chapter 6: Testbench 102
- Chapter 6: Testbench 6–5 103
- 6–6 Chapter 6: Testbench 104
- Chapter 6: Testbench 6–7 105
- 6–8 Chapter 6: Testbench 106
- A. Start-Up Sequence 107
- Troubleshooting 109
- Issues and Tips—Miscellaneous 111
- Separate PLLs 113
- Shared PLL 113
- "<rx_pll>" 114
- Note to Table C–1: 115
- D. Board Design 117
- Probe Points 118
- Spare Pins 119
- JTAG Scan Chain 119
- D–4 Appendix D: Board Design 120
- Design for Testability 120
- Introduction 121
- Static Alignment 125
- Dynamic Alignment 126
- Altera Solutions 126
- Dynamic Phase Alignment (DPA) 127
- AC Timing Analysis 128
- Budgets 129
- G. Conversion from v2.2.x 131
- Receiver Signals 132
- Transmitter Signals 134
- Additional Information 139
- Note to Table: 140
- Additional Information Info–3 141
- Typographic Conventions 141
- Info–4 Additional Information 142
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