Altera POS-PHY Level 4 IP Core manuales

Manuales del propietario y guías del usuario para Instrumentos de medición Altera POS-PHY Level 4 IP Core.
Ofrecemos 1 manuales en pdf Altera POS-PHY Level 4 IP Core para descargar gratis por tipos de documentos: Manual de usuario

Altera POS-PHY Level 4 IP Core Manual de usuario (142 paginas)

Marca: Altera | Categoria: Instrumentos de medición | Tamaño: 2.74 MB |

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User Guide

POS-PHY Level 4 IP Core

1. About This IP Core

General Description

Interfaces & Protocols

IP Core Verification

OpenCore Plus IP Evaluation

2. Getting Started

Using the Parameter Editor

Upgrading Outdated IP Cores

Specify Parameters

Simulate the Design

3. Parameter Settings

LVDS Data Rate

PLL Input Frequency

Data Path Width

Buffer Mode

Basic Parameters

Atlantic FIFO Buffer Clock

Atlantic Interface Width

Optional Features

Transmitter Options

Receiver Options

Starving Starving Starving

Starving Hungry Hungry

Starving Satisfied Satisfied

FIFO RAM Blocks

Note to Table 3–5:

Protocol Parameters

Features

Block Description

ALTLVDS_RX IP Core

Data Processor (rx_data_proc)

Atlantic Buffers

Individual Buffers

Status Processor

Notes to Figure 4–3:

Note to Table 4–1:

Notes to Figure 4–4:

Requirements for rxsys_clk

Reset Structure

Error Flagging and Handling

SPI-4.2 Protocol Errors

Notes to Table 4–3:

DIP-4 Marking

Notes to Figure 4–8:

Missing SOP

Missing EOP

Note to Table 4–7:

Note to Table 4–8:

Note to Table 4–9:

Latency Information

Data Processor (tx_data_proc)

Status Bypass Port

Clock Structure

Multiple Clock Domain

Notes to Figure 5–4:

Note to Table 5–5:

6. Testbench

Variation

100

Receiver

100

Receiver Testbench Examples

101

6–4 Chapter 6: Testbench

102

Chapter 6: Testbench 6–5

103

6–6 Chapter 6: Testbench

104

Chapter 6: Testbench 6–7

105

6–8 Chapter 6: Testbench

106

A. Start-Up Sequence

107

Troubleshooting

109

Issues and Tips—Miscellaneous

111

Separate PLLs

113

Shared PLL

113

"<rx_pll>"

114

Note to Table C–1:

115

D. Board Design

117

Probe Points

118

Spare Pins

119

JTAG Scan Chain

119

D–4 Appendix D: Board Design

120

Design for Testability

120

Introduction

121

Static Alignment

125

Dynamic Alignment

126

Altera Solutions

126

Dynamic Phase Alignment (DPA)

127

AC Timing Analysis

128

Budgets

129

G. Conversion from v2.2.x

131

Receiver Signals

132

Transmitter Signals

134

Additional Information

139

Note to Table:

140

Additional Information Info–3

141

Typographic Conventions

141

Info–4 Additional Information

142

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Altera POS-PHY Level 4 IP Core manuales

Altera POS-PHY Level 4 IP Core Manual de usuario (142 paginas)

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