Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Manual de usuario Pagina 88

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Figure 3-24: PTP Receive Block Diagram
RX
Adapter
RX
PCS
RX MAC
PTP_RX
TOD Module
rx_data
SoP
RX PMA
SOP
tod_rxmac_in
rx_tod
clk_rxmac
Related Information
IEEE website
The IEEE 1588-2008 Precision Clock Synchronization Protocol for Networked Measurement and Control
Systems Standard is available on the IEEE website.
PTP Transmit Functionality
When you send a 1588 PTP packet to a Low Latency 40-100GbE IP core with Enable 1588 PTP turned on
in the parameter editor, you must assert the tx_in_ptp signal with the TX SOP signal to tell the IP core
the incoming packet is a 1588 PTP packet. The IP core transmits the 1588 PTP packet in an Ethernet
frame with the appropriate one-step or two-step clock derived timestamp. The IP core is in one-step
mode if the ptp_s2 field of the TX_PTP_STATUS register has the value of 0. The IP core is in two-step mode
if this register field has the value of 1.
UG-01172
2015.05.04
PTP Transmit Functionality
3-43
Functional Description
Altera Corporation
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