Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Manual de usuario Pagina 102

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Table 3-17: Low Latency 40-100GbE MAC and PHY IP Core Signals
Signal Name Direction Interface
clk_ref
Input Clocks
clk_rx_recover Output Clocks
This signal is only available if
you turn on Enable SyncE in the
parameter editor.
reset_async
Input Reset
tx_serial[3:0] (40GbE and
CAUI–4)
tx_serial[9:0] (100GbE)
Output Transceiver PHY serial data
interface
rx_pcs_ready
Output
PHY status
tx_lanes_stable Output
clk_txmac_in Input
Clocks
Interface to external TX MAC
PLL
This signal is only available if
you turn on Enable external TX
MAC PLL in the parameter
editor.
clk_txmac
Output Clocks
TX client interface
l<n>_tx_data[<n>*64-1:0]
Input
Avalon-ST TX client interface
Each IP core instance has
Avalon-ST TX and RX client
interfaces, or custom streaming
TX and RX client interfaces.
l<n>_tx_empty[<l>-1:0]
Input
l<n>_tx_startofpacket
Input
l<n>_tx_endofpacket
Input
l<n>_tx_ready
Output
l<n>_tx_valid
Input
l<n>_tx_error Input
din[<w>*64-1:0]
Input
Custom streaming TX client
interface
din_sop[<w>-1:0]
Input
UG-01172
2015.05.04
Low Latency 40-100GbE IP Core Signals
3-57
Functional Description
Altera Corporation
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