Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Manual de usuario Pagina 123
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Address Name Bit Description HW
Reset
Value
Access
Updated RX
Coef new,
Lane 2
[10]
When set to 1, indicates that new local device
coefficients are available for Lane 2. The LT logic
changes the local TX equalizer coefficients as
specified in 0xE5[23:16]. When set to 0,
continues normal operation. This bit self clears.
This override of normal operation can only
occur if 0xD0[17] (Ovride Local RX Coef
enable) has the value of 1.
This bit is the equivalent of register 0xD1[9] for
Lane 2.
1'b0
RW
Updated RX
Coef new,
Lane 3
[11]
When set to 1, indicates that new local device
coefficients are available for lane 3. The LT logic
changes the local TX equalizer coefficients as
specified in 0xE9[23:16]. When set to 0,
continues normal operation. This bit self clears.
This override of normal operation can only
occur if 0xD0[17] (Ovride Local RX Coef
enable) has the value of 1.
This bit is the equivalent of register 0xD1[9] for
Lane 3.
1'b0
RW
0x0D2
Reserved
[7:6] Reserved
[13:8]
Register bits 0xD2[5:0] refer to Lane 0. These bits
are the equivalent of 0xD2[5:0] for Lane 1.
For Link Training Frame lock Error, Lane
1, if the tap settings specified by the fields of
0xE2 are the same as the initial parameter value,
the frame lock error was unrecoverable.
RO
[21:16
]
These bits are the equivalent of 0xD2[5:0] for
Lane 2.
For Link Training Frame lock Error, Lane
2, if the tap settings specified by the fields of
0xE6 are the same as the initial parameter value,
the frame lock error was unrecoverable.
RO
[29:24
]
These bits are the equivalent of 0xD2[5:0] for
Lane 3.
For Link Training Frame lock Error, Lane
3, if the tap settings specified by the fields of
0xEA are the same as the initial parameter value,
the frame lock error was unrecoverable.
RO
3-78
LL 40GBASE-KR4 Registers
UG-01172
2015.05.04
Altera Corporation
Functional Description
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Features 6
- Device Family Support 8
- IP Core Verification 9
- Simulation Environment 10
- Compilation Checking 10
- Hardware Testing 10
- Variation 11
- A B C D E F 11
- Parameter 11
- Release Information 14
- Getting Started 15
- OpenCore Plus IP Evaluation 17
- IP Core Parameters 19
- Parameter Type Range Default 23
- Parameter Description 23
- File Name Description 29
- Pin Assignments 32
- External TX MAC PLL 35
- File Names Description 38
- Initializing the IP Core 45
- Functional Description 46
- High Level System Overview 47
- Address Insertion 49
- Length/Type Field Processing 49
- Frame Padding 50
- Client Interface 51
- Data Bus Width (Bits) 51
- Three unusable words 57
- Order of Transmission 59
- RX CRC Forwarding 63
- Inter-Packet Gap 63
- Pause Ignore 63
- Control Frame Identification 64
- Name Direction Description 65
- Low Latency 100GbE CAUI–4 PHY 72
- External Transceiver PLL 72
- Pause Control Frame Filtering 76
- Statistics Counters Interface 79
- Name Signal 80
- Direction 80
- Description 80
- OctetOK Count Interface 82
- Transparent Clock Mode 85
- PTP Receive Functionality 87
- PTP Transmit Functionality 88
- 1588 PTP Interface Signals 90
- PTP Timestamp Formats 92
- PHY Status Interface 93
- Control and Status Interface 94
- Signal Name Description 97
- UG-01172 100
- 2015.05.04 100
- Related Information 108
- Software Interface: Registers 109
- PHY Registers 112
- LL 40GBASE-KR4 Registers 116
- Pause Registers 130
- TX Statistics Registers 137
- RX Statistics Registers 143
- 1588 PTP Registers 148
- Ethernet Glossary 150
- Term Definition 151
- Altera Corporation 153
- Send Feedback 153
- Arria 10 10GBASE-KR Registers 160
- 0x4D6 to 181
- MAC+PHY KR solution 181
- Subscribe 182
- Additional Information 187
- Date Compatible ACDS 188
- How to Contact Altera 194
- Typographic Conventions 195
- Visual Cue Meaning 196
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