Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Manual de usuario Pagina 54
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Signal Name Direction Description
l<n>_tx_error Input When asserted in an EOP cycle (while l<n>_tx_
endofpacket is asserted), directs the IP core to insert an
error in the packet before sending it on the Ethernet link.
This signal is a test and debug feature. In loopback mode,
the IP core recognizes the packet upon return as a
malformed packet.
Figure 3-4: Traffic on the TX and RX Avalon-ST Client Interface for Low Latency 40GbE IP Core
Shows typical traffic for the TX and RX Avalon-ST interface Low Latency 40GbE IP core.
l4_tx_data[255:0]
l4_tx_startofpacket
l4_tx_endofpacket
l4_tx_empty[4:0]
l4_tx_ready
l4_tx_valid
l4_rx_data[255:0]
l4_rx_startofpacket
l4_rx_endofpacket
l4_rx_empty[4:0]
l4_rx_valid
l4_rx_error[5:0]
2
.
2
.
2
.
2C83
.
2C8300392C8300382C
.
3
.
3
.
3
.
3
.
3
.
3EF9
.
3EF900553EF90054
.
3EF9
.
3EF9
00
0D 00
..
7B44
.
7B44
.
7B44
.
E
.
EFB8
.
EFB8
.
EFB8
.
EFB8
.
EFB8
.
EFB8
.
E
.
EAD
.
EAD2
.
EAD2
.
EAD
.
1E 02 1A
00
Figure 3-5: Traffic on the TX and RX Avalon-ST Client Interface for Low Latency 100GbE IP Core
Shows typical traffic for the TX and RX Avalon-ST interface of the 100GbE IP core.
l8_tx_data[511:0]
l8_tx_startofpacket
l8_tx_endofpacket
l8_tx_empty[5:0]
l8_tx_ready
l8_tx_valid
l8_rx_data[511:0]
l8_rx_startofpacket
l8_rx_endofpacket
l8_rx_empty[5:0]
l8_rx_valid
l8_rx_error[5:0]
.. . . . . . . . .
7CD901437CD901427C
. . . . . . . .
3BCA01273BCA01263BCA01253
. . . . .
00 2F 00 29 00
64
..
64
. .
A
. .
A
.
A
. .
A
. .
6
. .
6
. .
6E
.
6
.
07
. .
FF
. .
FF
.
07
. .
FD4
. .
0707070707070
30
.
30 10 30
.
22 02 22 0D 2E 0E
.
05
.
00
UG-01172
2015.05.04
Low Latency 40-100GbE IP Core TX Data Bus with Adapters (Avalon-ST Interface)
3-9
Functional Description
Altera Corporation
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Features 6
- Device Family Support 8
- IP Core Verification 9
- Simulation Environment 10
- Compilation Checking 10
- Hardware Testing 10
- Variation 11
- A B C D E F 11
- Parameter 11
- Release Information 14
- Getting Started 15
- OpenCore Plus IP Evaluation 17
- IP Core Parameters 19
- Parameter Type Range Default 23
- Parameter Description 23
- File Name Description 29
- Pin Assignments 32
- External TX MAC PLL 35
- File Names Description 38
- Initializing the IP Core 45
- Functional Description 46
- High Level System Overview 47
- Address Insertion 49
- Length/Type Field Processing 49
- Frame Padding 50
- Client Interface 51
- Data Bus Width (Bits) 51
- Three unusable words 57
- Order of Transmission 59
- RX CRC Forwarding 63
- Inter-Packet Gap 63
- Pause Ignore 63
- Control Frame Identification 64
- Name Direction Description 65
- Low Latency 100GbE CAUI–4 PHY 72
- External Transceiver PLL 72
- Pause Control Frame Filtering 76
- Statistics Counters Interface 79
- Name Signal 80
- Direction 80
- Description 80
- OctetOK Count Interface 82
- Transparent Clock Mode 85
- PTP Receive Functionality 87
- PTP Transmit Functionality 88
- 1588 PTP Interface Signals 90
- PTP Timestamp Formats 92
- PHY Status Interface 93
- Control and Status Interface 94
- Signal Name Description 97
- UG-01172 100
- 2015.05.04 100
- Related Information 108
- Software Interface: Registers 109
- PHY Registers 112
- LL 40GBASE-KR4 Registers 116
- Pause Registers 130
- TX Statistics Registers 137
- RX Statistics Registers 143
- 1588 PTP Registers 148
- Ethernet Glossary 150
- Term Definition 151
- Altera Corporation 153
- Send Feedback 153
- Arria 10 10GBASE-KR Registers 160
- 0x4D6 to 181
- MAC+PHY KR solution 181
- Subscribe 182
- Additional Information 187
- Date Compatible ACDS 188
- How to Contact Altera 194
- Typographic Conventions 195
- Visual Cue Meaning 196
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